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Localized Charge Trapping Memory Cells in a 63 nm Generation with Nanoscale Epitaxial Cobalt Salicide Buried Bitlines

  • Torsten Mueller (a1), C. Kleint (a2), C. Fitz (a3), M. Isler (a4), S. Riedel (a5), J.-U. Sachse (a6), D. Olligs (a7), H. Boubekeur (a8), F. Heinrichsdorf (a9), V. Polei (a10), D. Pritchard (a11), M. Verhoeven (a12), L. Lattard (a13), M. Markert (a14), C. Schupke (a15), B. Tippelt (a16), S. Teichert (a17), R. Reisdorf (a18), C. Ludwig (a19), E.G. Stein v. Kamienski (a20), T. Mikolajick (a21) and N. Nagel (a22)...

A 63nm Twin Flash memory cell with a size of 0.0225μm2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.

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  • EISSN: 1946-4274
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