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Low Defect Ceria for ILD CMP

Published online by Cambridge University Press:  01 February 2011

Jai Kasthurirangan
Affiliation:
jai_kasthurirangan@cabotcmp.com, Cabot Microelectronics Corporation, R & D, 870 N Commons Dr, Aurora, IL, 60504, United States, 630-499-2714
John Parker
Affiliation:
john_parker@cabotcmp.com, Cabot Microelectronics Corporation, 870 N Commons Dr, Aurora, IL, 60504, United States
Tiffany Bettis
Affiliation:
tiffany_bettis@cabotcmp.com, Cabot Microelectronics Corporation, 870 N Commons Dr, Aurora, IL, 60504, United States
Charles Dowell
Affiliation:
charles_dowell@cabotcmp.com, Cabot Microelectronics Corporation, 870 N Commons Dr, Aurora, IL, 60504, United States
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Abstract

The reduction of wafer scratching is a key goal driving the commercial development of CMP slurries. To better understand the underlying abrasive particle properties critical to the scratch performance of ILD CMP slurries, the scratching behavior of ceria slurries prepared with a range of particle size characteristics are characterized. Scratch results are presented and two effects are proposed to account for the findings. The Removal Rate Effect relies solely on the observed inverse proportionality between scratching and removal rate. This interpretation is consistent with a simple surface balance of scratches but suggests that removal rate differences dominate scratch performance. The Managed Tail Effect considers the effect of particle characteristics on both the creation and the removal of scratches. For a given particle population, the larger particles are assumed to dominate scratch creation. However, larger particles are also seen to drive removal rate which affects the removal of scratches during polishing. This interpretation implies that optimal scratch performance for a ceria ILD CMP slurry will be obtained when the width of the ceria particle's size distribution is optimized relative to its mean.

Keywords

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

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References

REFERENCES

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