In the next decade, it is expected that integrated circuits having 5 to 7 levels of metal will be common in VLSI technologies with linear interconnect densities approaching 200 meters/cm2/level. Multilevel interconnect technology needs are presently generating processing and structural issues which will dominate the future manufacturing yield and performance of these integrated circuits. The challenge of meeting these needs will require a concurrent improvement in design and manufacturing simplicity and cleanliness. This presentation will examine the architectural needs of future multilevel metal systems in light of the lithography, materials, and electrical requirements which must be addressed by the interconnect engineer. A comparison of interconnect systems based on different conductor materials will be presented.
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