Skip to main content
×
×
Home

Materials Aspects to Consider in the Fabrication of Through-Silicon Vias

  • Susan Burkett (a1), L. Schaper (a2), T. Rowbotham (a3), J. Patel (a4), T. Lam (a5), I. U. Abhulimen (a6), D. D. Boyt (a7), M. Gordon (a8) and L. Cai (a9)...
Abstract

The formation of vertical interconnects to create three-dimensional (3D) interconnects enables integration of dissimilar electronic material technologies. These vertical interconnects are metal filled blind vias etched in silicon and are formed by a series of processing steps that include: silicon etch; insulation/barrier/seed layer deposition; electroplating of Cu to fill the via; wafer grinding and thinning; and back side processing to form contacts. Deep reactive ion etching (DRIE) is used to etch silicon vias with attention given to process parameters that affect sidewall angle, sidewall roughness, and lateral etch growth at the top of the via. After etching, vias are insulated by depositing 0.5 μm of silicon dioxide by plasma enhanced chemical vapor deposition (PECVD) at 325°C. A barrier film of TaN is reactively sputtered after insulation deposition followed by a Cu sputtered seed film allowing electroplated Cu to fill the blind via. Reverse pulse plating is used to achieve bottom-up filling of the via. Once void-free electroplated vias are prepared, the process wafer is attached to a carrier wafer for silicon back grinding. Vias on the process wafer are “exposed” from the back side of the wafer with a combination of processes that include mechanical grinding, polishing, and reactive ion etching (RIE). Contact pads are then formed by conventional IC processes. Cu posts are used to connect the electronic devices and to address thermal management issues as well. This paper presents materials aspects to consider when fabricating through silicon vias (TSVs). Modeling of the Cu-filled vias to investigate thermal management schemes and Cu posts to investigate mechanical reliability is also presented.

Copyright
References
Hide All
1. International Technology Roadmap for Semiconductors (ITRS) (2004).
2. Peters, L., Semiconductor International, September issue (2006).
3. Davis, J., Semiconductor International, August issue (2006).
4. Bower, C. A., Malta, D., Temple, D., Robinson, J. E., Coffman, P. R., Skokan, M. R., and Welch, T. B., IEEE Proc. ECTC, 399 (2006).
5. Andry, P. S., Tsang, C., Sprogis, E., Patel, C., Wright, S. L., Webb, B. C., Buchwalter, L. P., Manzer, D., Horton, R., Polastre, R., and Knickerbocker, J., IEEE Proc. ECTC, 831 (2006).
6. Schaper, L., Burkett, S., Spiesshoefer, S., Vangara, G., Rahman, Z., and Polamreddy, S., IEEE Trans. Advanced Packaging, Vol. 28, No. 3, 356 (2005).
7. Lu, J.-Q., Lee, K.W., Kwon, Y., Rajagopalan, G., McMahon, J., Altemus, B., Gupta, M., Eisenbraun, E., Xu, B., Jindal, A., Kraft, R.P., McDonald, J.F., Castracane, J., Cale, T.S., and Kaloyeros, A., and Gutmann, R.J., Proc. Advanced Metallization Conference (AMC), San Diego, CA (2002).
8. Kim, S. K. K. and Tiwari, S., IEEE Proc. International Conf. Integrated Circuit and Technology, 183 (2005).
9. Miranda, P. A. and Moll, A. J., IEEE Proc. ECTC, 844 (2006).
10. Cong, J., Jagannathan, A., Ma, Y., Reinman, G., Wei, J., and Zhang, Y., Proc. IEEE Conf. Design Automation, 384 (2006).
11. Abhulimen, I. U., Polamreddy, S., Burkett, S., Cai, L., and Schaper, L., J. Vac. Sci. Technol. A, manuscript in preparation.
12. Gomez, S., Belen, R. Jun, Kiehlbauch, M., Aydil, E. S., J. Vac. Sci. Technol. A, 22 (3), 606 (2004).
13. Abdolvand, R. and Ayazi, F., Proc. IEEE MEMS Conf., 151 (2005).
14. Rossnagel, S. M., J. Vac. Sci. Technol. B, 20 (6), 2328 (2002).
15. Tsai, M. H., Sun, S. C., Tsai, C. E., Chuang, S. H., and Chiu, H. T., J. Appl. Phys., 79 (9), 6932 (1996).
16. Rowbotham, T., Patel, J., Lam, T., Burkett, S., Cai, L., and Schaper, L., J. Vac. Sci. Technol. B, 24 (5), 2460 (2006).
17. Ranganathan, N., Prasad, K., Balasubramanian, N., Qiaoer, Z., and Hwee, S.C., IEEE Proc. ECTC, 343 (2005).
Recommend this journal

Email your librarian or administrator to recommend adding this journal to your organisation's collection.

MRS Online Proceedings Library (OPL)
  • ISSN: -
  • EISSN: 1946-4274
  • URL: /core/journals/mrs-online-proceedings-library-archive
Please enter your name
Please enter a valid email address
Who would you like to send this to? *
×

Keywords