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Materials Aspects to Consider in the Fabrication of Through-Silicon Vias

Published online by Cambridge University Press:  26 February 2011

Susan Burkett ,
L. Schaper ,
T. Rowbotham ,
J. Patel ,
T. Lam ,
I. U. Abhulimen ,
D. D. Boyt ,
M. Gordon  and
L. Cai
Susan Burkett
Affiliation:
sburkett@nsf.gov, University of Arkansas, Electrical Engineering, 3217 Bell Engineering Center, Fayetteville, AR, 72701, United States, 479-575-6048, 479-575-7967
L. Schaper
Affiliation:
schaper@uark.edu, University of Arkansas, Electrical Engineering, Fayetteville, AR, 72701, United States
T. Rowbotham
Affiliation:
trowbot@uark.edu, University of Arkansas, Electrical Engineering, Fayetteville, AR, 72701, United States
J. Patel
Affiliation:
jpatel@uark.edu, University of Arkansas, Electrical Engineering, Fayetteville, AR, 72701, United States
T. Lam
Affiliation:
tqlam@uark.edu, University of Arkansas, Electrical Engineering, Fayetteville, AR, 72701, United States
I. U. Abhulimen
Affiliation:
iumolua@uark.edu, University of Arkansas, Electrical Engineering, Fayetteville, AR, 72701, United States
D. D. Boyt
Affiliation:
dboyt@uark.edu, University of Arkansas, Mechanical Engineering, Fayetteville, AR, 72701, United States
M. Gordon
Affiliation:
mhg@uark.edu, University of Arkansas, Mechanical Engineering, Fayetteville, AR, 72701, United States
L. Cai
Affiliation:
lcai@uark.edu, University of Arkansas, Electrical Engineering, Fayetteville, AR, 72701, United States
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Abstract

The formation of vertical interconnects to create three-dimensional (3D) interconnects enables integration of dissimilar electronic material technologies. These vertical interconnects are metal filled blind vias etched in silicon and are formed by a series of processing steps that include: silicon etch; insulation/barrier/seed layer deposition; electroplating of Cu to fill the via; wafer grinding and thinning; and back side processing to form contacts. Deep reactive ion etching (DRIE) is used to etch silicon vias with attention given to process parameters that affect sidewall angle, sidewall roughness, and lateral etch growth at the top of the via. After etching, vias are insulated by depositing 0.5 μm of silicon dioxide by plasma enhanced chemical vapor deposition (PECVD) at 325°C. A barrier film of TaN is reactively sputtered after insulation deposition followed by a Cu sputtered seed film allowing electroplated Cu to fill the blind via. Reverse pulse plating is used to achieve bottom-up filling of the via. Once void-free electroplated vias are prepared, the process wafer is attached to a carrier wafer for silicon back grinding. Vias on the process wafer are “exposed” from the back side of the wafer with a combination of processes that include mechanical grinding, polishing, and reactive ion etching (RIE). Contact pads are then formed by conventional IC processes. Cu posts are used to connect the electronic devices and to address thermal management issues as well. This paper presents materials aspects to consider when fabricating through silicon vias (TSVs). Modeling of the Cu-filled vias to investigate thermal management schemes and Cu posts to investigate mechanical reliability is also presented.

Keywords

CuelectrodepositionSi
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y06-01
Copyright
Copyright © Materials Research Society 2007

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