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A New Offset Gated Poly-Si TFT Using a Wet Oxidation

Published online by Cambridge University Press:  15 February 2011

B.H. Min
Affiliation:
Department of Electrical Engineering, Seoul National University, San 56–1, Shinrim-dong, Kwanak-ku, Seoul 151–742, Korea
J.M. Oh
Affiliation:
Department of Electrical Engineering, Seoul National University, San 56–1, Shinrim-dong, Kwanak-ku, Seoul 151–742, Korea
M.K. Han
Affiliation:
Department of Electrical Engineering, Seoul National University, San 56–1, Shinrim-dong, Kwanak-ku, Seoul 151–742, Korea
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Abstract

Several off-set gated TFTs have been proposed to reduce the off current. However, those structures may require an additional mask and photolithography process step. We propose a novel off-set gated poly-Si TFT which reduces the off current considerably without any additional mask.

We have simulated the device characteristics by a numerical simulator in order to verify the proposed TFT. The simulation results show that the off current of the new device has been reduced to 0.ipA. The reduction of on current is much less than the off current reduction and the on/off current ratios exceeding 107 have been accomplished.

Type
Research Article
Copyright
Copyright © Materials Research Society 1994

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References

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