Hostname: page-component-8448b6f56d-tj2md Total loading time: 0 Render date: 2024-04-19T11:56:12.038Z Has data issue: false hasContentIssue false
  • English
  • Français

Optimizing the Screen-Grid Field Effect Transistor for high drive current and low Miller capacitance

Published online by Cambridge University Press:  31 January 2011

Yasaman Shadrokh ,
Kristel Fobelets  and
Enrique Velazquez-Perez
Yasaman Shadrokh
Affiliation:
y.shadrokh@imperial.ac.uk, Imperial College, Electronic and Electrical Engineering, London, United Kingdom
Kristel Fobelets
Affiliation:
k.fobelets@imperial.ac.uk, Imperial College, Electronic and Electrical Engineering, London, United Kingdom
Enrique Velazquez-Perez
Affiliation:
js@usal.es, Universidad de Salamanca, Departmento de Física Aplicada, Salamanca, Spain
Get access

Abstract

Reduction of parasitic capacitances and improvement of the on-off current ratio (ION/IOFF) can be achieved by increasing the gate control in Field Effect Transistors (FETs). Multiple gated FETs (MugFETs) lend themselves well for this. The MugFET investigated in this manuscript is the Screen Grid FET (SGrFET) that consists of multiple gate cylinders inside the channel perpendicular to the current flow. In this work we illustrate, using 2D Technology Computer Aided Design (TCAD), that the multiple geometrical degrees of freedom of the SGrFET can be exploited to simultaneously optimise the on-current, ION and the gate-drain Miller parasitic capacitance for increased switching speed.

Keywords

electrical propertiesnanostructuresimulation
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1174: Symposium V – Functional Metal-Oxide Nanostructures , 2009 , 1174-V09-36
Copyright
Copyright © Materials Research Society 2009

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1 Fobelets, K. Ding, P.W.., and Velazquez-Perez, J. E., A novel 3D Gate Field Effect Transistor Screen-Grid FET Device-Concept and Modelling. Solid State Electron, 2007. 51 (5): p. 749–759.Google Scholar
2 Ding, P. W. Fobelets, K.., and Velazquez-Perez, J.E., Analog Performance of Screen Grid Field Effect Transistor (SGrFET). WOFE, Cozumel (Mexico) 2007.Google Scholar
3 Taurus-Medici User Guide (Version W-2004.09), S.I., Mountain View, CA.Google Scholar
4 Andreev, B. Titlebaum, E. L. and Friedman, E. G.., Sizing CMOS Inverter with Miller Effect and Threshold voltage Variations. World Science, 2006. 15(5): p. 437–454.Google Scholar
5 Shadrokh, Y. Fobelets, K.., and Velazquez-Perez, J. E., Single Device Logic using 3D Gating of Screen Grid Feild Effect Transistor Logic. Semiconductor Conference, 2007. CAS 2007. International, October 2007. 1: p. 45–48.Google Scholar