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Pattern Dependent Modeling for CMP Optimization and Control

Published online by Cambridge University Press:  10 February 2011

D. Boning ,
B. Lee ,
C. Oji ,
D. Ouma ,
T. Park ,
T. Smith  and
T. Tugbawa
D. Boning
Affiliation:
Massachusetts Institute of Technology, Microsystems Technology Laboratories, EECS, Room 39–567, Cambridge, MA 02139
B. Lee
Affiliation:
Massachusetts Institute of Technology, Microsystems Technology Laboratories, EECS, Room 39–567, Cambridge, MA 02139
C. Oji
Affiliation:
Massachusetts Institute of Technology, Microsystems Technology Laboratories, EECS, Room 39–567, Cambridge, MA 02139
D. Ouma
Affiliation:
Massachusetts Institute of Technology, Microsystems Technology Laboratories, EECS, Room 39–567, Cambridge, MA 02139
T. Park
Affiliation:
Massachusetts Institute of Technology, Microsystems Technology Laboratories, EECS, Room 39–567, Cambridge, MA 02139
T. Smith
Affiliation:
Massachusetts Institute of Technology, Microsystems Technology Laboratories, EECS, Room 39–567, Cambridge, MA 02139
T. Tugbawa
Affiliation:
Massachusetts Institute of Technology, Microsystems Technology Laboratories, EECS, Room 39–567, Cambridge, MA 02139
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Abstract

In previous work, we have formalized the notions of “planarization length” and “planarization response function” as key parameters that characterize a given CMP consumable set and process. Once extracted through experiments using carefully designed characterization mask sets, these parameters can be used to predict polish performance in CMP for arbitrary product layouts. The methodology has proven effective at predicting oxide interlevel dielectric planarization results.

In this work, we discuss extensions of layout pattern dependent CMP modeling. These improvements include integrated up and down area polish modeling; this is needed to account for both density dependent effects, and step height limits or step height perturbations on the density model. Second, we discuss applications of the model to process optimization, process control (e.g. feedback compensation of equipment drifts), and shallow trench isolation (STI) polish. Third, we propose a framework for the modeling of pattern dependent effects in copper CMP. The framework includes “removal rate diagrams” which concisely capture dishing height and step height dependencies in dual material polish processes.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 566: Symposium P – Chemical-Mechanical Poilshing-Fundamentals and Challenges , 1999 , 197
Copyright
Copyright © Materials Research Society 2000

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References

REFERENCES

1. Stine, B., Ouma, D., Divecha, R., Boning, D., Chung, J., Hetherington, D., Ali, I., Shinn, G., Clark, J. Nakagawa, O. S., Oh, S.-Y, “A Closed-Form Analytic Model for ILD Thickness Variation in CMP Processes,” Proc. CMP-MIC Conf., Santa Clara, CA, Feb 1997.Google Scholar
2. Stine, B., Ouma, D., Divecha, R., Boning, D., Chung, J., Hetherington, D., Harwood, C. R., Nakagawa, O. S., and Oh, S.-Y, “Rapid Characterization and Modeling of Pattern Dependent Variation in Chemical Mechanical Polishing,” IEEE Trans. on Semi. Manuf., vol 11, no. 1 pp. 129–140, Feb 1998.Google Scholar
3. Ouma, D., Boning, D., Chung, J., Shinn, G., Olsen, L., and Clark, J., “An Integrated Characterization and Modeling Methodology for CMP Dielectric Planarization,” International Interconnect Technology Conference, San Francisco, CA, June 1998.Google Scholar
4. Boning, D., Ouma, D., and Chung, J., “Extraction of Planarization Length and Response Function in Chemical-Mechanical Polishing,” Materials Research Society 1998 Spring Meeting, San Francisco, CA, May 1998.Google Scholar
5. Grillaert, J., Meuris, M., Heylen, N., Devriendt, K., Vrancken, E., and Heyns, M., “Modelling step height reduction and local removal rates based on pad-substrate interactions,” CMP-MIC, pp. 79–86, Feb. 1998.Google Scholar
6. Burke, P. A., “Semi-empirical modeling of Si0 2 chemical-mechanical polishing planarization,” Proc. VMIC Conf., pp. 379–384, Santa Clara, CA, June 1991.Google Scholar
7. Tseng, E., Yi, C., and Chen, H. C., “A Mechanical Model for DRAM Dielectric Chemical- Mechanical Polishing Process,” CMP-MIC, pp. 258–265, Santa Clara, CA, Feb. 1997.Google Scholar
8. Smith, T. H., Boning, D., Fang, S. J., Shinn, G. B., and Stefani, J. A., “A CMP Model Combining Density and Time Dependencies,” Proc. CMP-MIC, Santa Clara, CA, Feb. 1999.Google Scholar
9. Grillaert, J., Meuris, M., Vrancken, E., Devriendt, K., Fyen, W., and Heyns, M., “Modelling the Influence of Pad Bending on the Planarization Performance During CMP,” Materials Research Society 1999 Spring Meeting, San Francisco, CA, April 1999.Google Scholar
10. Smith, T., Boning, D., Moyne, J., Hurwitz, A., and Curry, J., “Compensating for CMP Pad Wear Using Run by Run Feedback Control,” VLSI Multilevel Interconnect Conference, pp. 437–440, Santa Clara, CA, June 1996.Google Scholar
11. Boning, D., Hurwitz, A., Moyne, J., Moyne, W., Shellman, S., Smith, T., Taylor, J., and Telfeyan, R., “Run by Run Control of Chemical Mechanical Polishing,” IEEE Trans. on Components, Packaging, and Manufacturing Technology - Part C, Vol. 19, No. 1, pp. 307–314, Oct. 1996.10.1109/3476.558560Google Scholar
12. Smith, T., Fang, S. J., Stefani, J. A, Shinn, G. B., Boning, D. S., and Butler, S. W., “On-line Patterned Wafer Thickness Control of Chemical-Mechanical Polishing,” submitted to Journal of Vacuum Science and Technology A, November 1998.10.1116/1.581824Google Scholar
13. Smith, T., Fang, S., Stefani, J., Shinn, G., Boning, D. and Butler, S., “Device Independent Process Control of Chemical-Mechanical Polishing,” Process Control, Diagnostics, and Modeling in Semiconductor Device Manufacturing III, 195th Electrochemical Society Meeting, Seattle, WA, May 1999.Google Scholar
14. Pan, J. T., Ouma, D., Li, P., Boning, D., Redecker, F., Chung, J., and Whitby, J., “Planarization and Integration of Shallow Trench Isolation,” VLSI Multilevel Interconnect Conference, Santa Clara, CA, June 1998.Google Scholar
15. Ramarajana, S. and Babu, S.V., “Modified Preston Equation For Metal Polishing: Revisited,” Materials Research Society 1999 Spring Meeting, San Francisco, CA, April 1999.Google Scholar
16. Elbel, N., Neureither, B., Ebersberger, B., and Lahnor, P., “Tungsten Chemical Mechanical Polishing,” J. Electrochem. Soc., Vol. 145, No. 5, pp. 1659–1164, May 1998.10.1149/1.1838533Google Scholar
17. Grillaert, J., Meuris, M., Heylen, N., Devriendt, K., Vrancken, E., and Heyns, M., “Modelling step height reduction and local removal rates based on pad-substrate interactions,” Materials Research Society 1998 Spring Meeting, San Francisco, CA, May 1998.Google Scholar
18. Park, T., Tugbawa, T., Yoon, J., Boning, D., Chung, J., Muralidhar, R., Hymes, S., Gotkis, Y., Alamgir, S., Walesa, R., Shumway, L., Wu, G., F Zhang, Kistler, R., and Hawkins, J., “Pattern and Process Dependencies in Copper Damascene Chemical Mechanical Polishing Processes,” VLSI Multilevel Interconnect Conference, Santa Clara, CA, June 1998.Google Scholar
19. Park, T., Tugbawa, T., Boning, D., Chung, J., Hymes, S., Muralidhar, R., Wilks, B., Smekalin, K., Bersuker, G., “Electrical Characterization of Copper Chemical Mechanical Polishing,” Proc. CMP-MIC, Santa Clara, CA, Feb. 1999.Google Scholar
20. Hymes, S., Smekalin, K., Brown, T., Yeung, H., Joffe, M., Banet, M., Park, T., Tugbawa, T., Boning, D., Nguyen, J., West, T., and Sands, W., “Determination of the Planarization Distance for Copper CMP Process,” Materials Research Society 1999 Spring Meeting, San Francisco, CA, April 1999.Google Scholar