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Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors

  • Mustafa B. Akbulut (a1), Helena Silva (a1) and Ali Gokirmak (a1)
Abstract
ABSTRACT

Accumulated body [1] approach to mitigate the effects of line edge roughness on bulk silicon finFETs and tri-gate FETs is analyzed through 3D TCAD simulations. A side-gate surrounding the body portion of the FET is used to accumulate the body with majority carriers. This approach is predicted to reduce device-to-device variability due to line edge roughness by stronger accumulation of the body in the wider sections of the channel and confinement of the channel away from the edges.

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  • EISSN: 1946-4274
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