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Performance analysis of a-Si:H detectors deposited on CMOS chips

Published online by Cambridge University Press:  21 March 2011

C. Miazza
Affiliation:
Institut de Microtechnique, CH-2000 Neuchâtel, Switzerland
S. Dunand
Affiliation:
Institut de Microtechnique, CH-2000 Neuchâtel, Switzerland
N. Wyrsch
Affiliation:
Institut de Microtechnique, CH-2000 Neuchâtel, Switzerland
A. Shah
Affiliation:
Institut de Microtechnique, CH-2000 Neuchâtel, Switzerland
N. Blanc
Affiliation:
CSEM SA, CH-8048 Zurich, Switzerland
R. Kaufmann
Affiliation:
CSEM SA, CH-8048 Zurich, Switzerland
L. Cavalier
Affiliation:
CSEM SA, CH-8048 Zurich, Switzerland
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Abstract

Image and particle sensors based on thin-film on CMOS technology are currently being developed at our laboratory. In this technology, amorphous silicon detectors are vertically integrated on top of dedicated CMOS chips. For both, vision and particle detection, this approach is expected to enhance the performances. In fact very high fill factors, increased sensitivity, and integration level, coupled with extremely low dark current density values can potentially be attained.

A first optimization of the a-Si:H diodes (>1mm2) on glass substrates, with the primary focus on reducing dark current densities, gave Jdark values as low as 1 pA/cm2 (at -1 V for 1 m thick detectors). These detectors were then deposited on CMOS readout chips, but so far this step was unfortunately accompanied by an increase in Jdark to values over 10 nA/cm2.

Here, the possible cause for such an increase in Jdark as well as possible “remedies” against this effect will be discussed; the principle cause is supposed to be the influence of chip topology. Possible solutions include surface treatments as well as the use of metal-i-p diode configuration. Results obtained so far with these methods are given.

Type
Research Article
Copyright
Copyright © Materials Research Society 2004

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References

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