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Post-Annealing Effect on the Reliability of Ultra-Thin Silicon Dioxide with Polysilicon Gate

Published online by Cambridge University Press:  21 February 2011

Kenji Yoneda
Affiliation:
Kyoto Research Laboratory, Matsushita Electronics Corporation, 19, Nishikujo-Kasugacho, Minami-ku, Kyoto 601, JAPAN
Yoshiki Fukuzaki
Affiliation:
Kyoto Research Laboratory, Matsushita Electronics Corporation, 19, Nishikujo-Kasugacho, Minami-ku, Kyoto 601, JAPAN
Kazuo Satoh
Affiliation:
Kyoto Research Laboratory, Matsushita Electronics Corporation, 19, Nishikujo-Kasugacho, Minami-ku, Kyoto 601, JAPAN
Yoshjhiro Todokoro
Affiliation:
Kyoto Research Laboratory, Matsushita Electronics Corporation, 19, Nishikujo-Kasugacho, Minami-ku, Kyoto 601, JAPAN
Morio Inoue
Affiliation:
Kyoto Research Laboratory, Matsushita Electronics Corporation, 19, Nishikujo-Kasugacho, Minami-ku, Kyoto 601, JAPAN
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Abstract

Time dependent dielectric breakdown (TDDB) characteristics and TEM observation of ultra-thin silicon dioxide with the polysilicon gate after post-annealing and oxidation at 1000-1100 °C are discussed. The high temperature post-annealing decreases the TDDB characteristics of ultra-thin oxide with polysilicon gate. The charge to breakdown is reduced drastically with increasing the annealing temperature and annealing time. The dielectric breakdown reliability degradation of ultra-thin tunneling oxide by the post-annealing can be explained as the partial oxide thinning and electric field concentration due to the increase of roughness at the polysilicon gate/ultra-thin tunneling oxide interface. This increase of roughness is due to the grain growth of polysilicon gate and viscous flow of oxide, which are enhanced with increasing the annealing temperature and time.

Type
Research Article
Copyright
Copyright © Materials Research Society 1990

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