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Process and Manufacturing Challenges for High-K Gate Stack Systems

  • M.C. Gilmer (a1), T-Y Luo (a1), H.R. Huff (a1), M.D. Jackson (a1), S. Kim (a1), G. Bersuker (a1), P. Zeitzoff (a1), L. Vishnubhotla (a1), G.A. Brown (a1), R. Amos (a1), D. Brady (a1), V.H.C. Watt (a1), G. Gale (a1), J. Guan (a1), B. Nguyen (a1), G. Williamson (a1), P. Lysaght (a1), K. Torres (a1), F. Geyling (a1), C.F.H. Gondran (a1), J. A. Fair (a2), M.T. Schulberg (a2) and T. Tamagawa (a3)...


A design-of-experiments methodology was implemented to assess the commercial equipment viability to fabricate the high-K dielectrics Ta2O5, TiO2 and BST (70/30 and 50/50 compositions) for use as gate dielectrics. The high-K dielectrics were annealed in 100% or 10% O2 for different times and temperatures in conjunction with a previously prepared NH3 nitrided or 14N implanted silicon surface. Five metal electrode configurations—Ta, TaN, W, WN and TiN—were concurrently examined. Three additional silicon surface configurations were explored in conjunction with a more in-depth set of time and temperature anneals for Ta2O5. Electrical characterization of capacitors fabricated with the above high-K gate dielectrics, as well as SIMS and TEM analysis, indicate that the post high-K deposition annealing temperature was the most significant variable impacting the leakage current density, although there was minimal influence on the capacitance. Further studies are required, however, to clarify the physical mechanisms underlying the electrical data presented.



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