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Screening the High-k Layer Quality by Means of Open Circuit Potential Analysis and Wet Chemical Etching

Published online by Cambridge University Press:  11 February 2011

Martine Claes ,
Stefan De Gendt ,
Thomas Witters ,
Vidya Kaushik ,
Jerry Chen ,
Thierry Conard ,
Annelies Delabie ,
Sven Van Elshocht  and
Marc Heyns
Martine Claes
Affiliation:
IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium
Stefan De Gendt
Affiliation:
IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium
Thomas Witters
Affiliation:
IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium
Vidya Kaushik
Affiliation:
ISMT Industrial Affiliate at IMEC
Jerry Chen
Affiliation:
ISMT Industrial Affiliate at IMEC
Thierry Conard
Affiliation:
IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium
Annelies Delabie
Affiliation:
IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium
Sven Van Elshocht
Affiliation:
IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium
Marc Heyns
Affiliation:
IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium
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Abstract

A fast way to monitor the quality of high-k dielectric layers is wet etching, either monitored by Open Circuit Potential analysis or by Scanning Electron Microscopy. Defect densities in the order of 1.109 defects/cm2 are observed for as-deposited HfO2 layers. It is assumed that the mechanism for wet chemical defect observation is either due to crystallization and/or due to an oxygen deficient HfO2 layer resulting in Si/SiO up-diffusion upon thermal treatment. However, after appropriate post deposition annealing wet etch defect free layers can be prepared.

Information

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 745: Symposium N – Novel Materials and Processes for Advanced CMOS , 2002 , N1.8
Copyright
Copyright © Materials Research Society 2003

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References

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