In rapidly growing market sectors, such as mobile information devices, SiP technology, in which multiple LSI chips are stacked three-dimensionally, is attracting attention as a means of greatly reducing the mounting area of electronic components to improve system performance while reducing system size. Hitachi, Ltd. and Renesas Technology developed a new way to interconnect stacked chips using through-hole electrodes with a lower cost and shorter turn around time (TAT). Stacked chips are electrically interconnected by simply applying a compressive force at room temperature to a conventional chip with multiple gold stud bumps. Gold stud bumps on the upper chips are pressed into the through-hole electrodes on the lower chips by applying a compressive force, which causes plastic to flow into the gold bump. That is, the use of a gmechanical caulkingh technique makes possible electrical connections between stacked chips at room temperature. Compared with conventional through-hole electrode interconnection (more than 200°C), this new method drastically reduces the production cost and the environmental load. By using this technology, the package thickness can be 1.0 mm or less even in ten-chip layers, compared with two-chip layers using wire bonding, which are approximately 1.25-mm thick.
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