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Silicon Through-hole Interconnection for 3D-SiP Using Room Temperature Bonding

  • Naotaka Tanaka (a1), Yasuhiro Yoshimura (a2), Takahiro Naito (a3) and Takashi Akazawa (a4)
Abstract
ABSTRACT

In rapidly growing market sectors, such as mobile information devices, SiP technology, in which multiple LSI chips are stacked three-dimensionally, is attracting attention as a means of greatly reducing the mounting area of electronic components to improve system performance while reducing system size. Hitachi, Ltd. and Renesas Technology developed a new way to interconnect stacked chips using through-hole electrodes with a lower cost and shorter turn around time (TAT). Stacked chips are electrically interconnected by simply applying a compressive force at room temperature to a conventional chip with multiple gold stud bumps. Gold stud bumps on the upper chips are pressed into the through-hole electrodes on the lower chips by applying a compressive force, which causes plastic to flow into the gold bump. That is, the use of a gmechanical caulkingh technique makes possible electrical connections between stacked chips at room temperature. Compared with conventional through-hole electrode interconnection (more than 200°C), this new method drastically reduces the production cost and the environmental load. By using this technology, the package thickness can be 1.0 mm or less even in ten-chip layers, compared with two-chip layers using wire bonding, which are approximately 1.25-mm thick.

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References
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1. Koyanagi K., “Future System-on-Silicon LSI Chip,IEEE Micro, Vol. 18, No. 4, 1988, pp. 1722.
2. Takahashi K., “Development of Ultra Fine Pitch 3D Chip Stacking Module,” 7th Ann. Int. KGD Packaging and Test Workshop, 2000, pp. 336352.
3. Suga T., “Feasibility of Surface Activated Bonding for Ultra-fine Pitch interconnection-A New Concept of Bumpless Direct Bonding for System Level Packaging,” Proc. of 50th Electronic Components and Technology Conf, 2000, pp. 702705.
4. Sogawa Y., Yamazaki T., Hazeyama I., and Kitajo S., “Reliability of an Ultra-high-density 3-dimensional-stacked Package ‘FFCSP,’” Proc. of International Conference on Electronics Packaging, Japan, Apr. 2004, pp. 4146.
5. Tanaka N., Yoshimura Y., Naito T., Miyazaki C., Nemoto Y., Nakanishi M., and Akazawa T., “Ultra-Thin 3D-Stacked SIP Formed using Room-Temperature Bonding between Stacked Chips,” Proc. of 55th Electronic Components and Technology Conf, 2005, pp. 788794.
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  • EISSN: 1946-4274
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