Superlattices with an ultra-low thermal conductivity were extensively studied to design thermoelectric materials. However, since they are made up of superposed materials showing lattice mismatches, they often show cracks and dislocations. Therefore, it is challenging to fabricate superlattices with a thermoelectric figure of merit ZT higher than unity. Moreover, like nanowires, they decrease heat transport in only one main direction. Self-assembly from epitaxial layers on a Si substrate is a major bottom-up technology to fabricate 3D Ge quantum-dot (QD) arrays in Si, which have been used for 3D quantum-device applications. Using the model of the atomic-scale 3D phononic crystal, we showed that 3D high-density arrays of self-assembled Ge QDs in Si can also show an ultra-low thermal conductivity in 3D, which can be several orders of magnitude lower than that of bulk Si. As a result, they can be considered to design novel 3D thermoelectric devices showing CMOS compatibility. In an example QD crystal, the thermal conductivity can be decreased below only 0.2 W/m/K. The main objective of this paper is to show the size dependence of the thermal conductivity versus the supercell lattice parameter d. For a constant QD-crystal filling ratio x = 12.5 at%, a decrease of the thermal conductivity is observed for an increasing d. This analysis enables us to predict that the optimal d-value will be of the order of 11 nm for the given filling ratio. At this optimum, the thermal conductivity decreases to the global minimum value of 0.9 W/m/K. The presented results are a first step towards the optimal design of thermoelectric devices with a maximal ZT obtained by global optimization of the size parameters.
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