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A Study on STI and Damascene CMP using Chip Level Simulation

Published online by Cambridge University Press:  18 March 2011

Kyung-Hyun Kim ,
Yoo-Hyon Kim ,
Kwang-Bok Kim ,
Chang-Ki Hong  and
Moon-Hyun Yoo
Kyung-Hyun Kim
Affiliation:
Process Development Team
Yoo-Hyon Kim
Affiliation:
CAE, Semi. R&D Center, Samsung Electronics Co., Ltd. San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do, KOREA Tel: 82-2-760-5289, Fax: 82-2-760-6120, E-mail: hyuncmp@samsung.co.kr
Kwang-Bok Kim
Affiliation:
Process Development Team
Chang-Ki Hong
Affiliation:
Process Development Team
Moon-Hyun Yoo
Affiliation:
CAE, Semi. R&D Center, Samsung Electronics Co., Ltd. San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do, KOREA Tel: 82-2-760-5289, Fax: 82-2-760-6120, E-mail: hyuncmp@samsung.co.kr
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Abstract

Simulation of chemical-mechanical polishing is important because the chip-level planarity are difficult to control. The simulator has been developed for predicting and optimizing the thickness distribution after the STI and damascene CMP as well as ILD CMP using chip-level pattern density, elastic spring model and erosion model. In this study, the results of CMP simulation is shown to agree well with the measured data. The simulator can be used to optimize CMP process conditions and to generate design rules for filling dummy patterns which are used to improve the planarity and uniformity.

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References

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