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Sub-Half Micron Elevated SourceDrain NMOSFETS by Low Temperature Selective Epitaxial Deposition

Published online by Cambridge University Press:  10 February 2011

J. Sun
Affiliation:
Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695
R. F. Bartholomew
Affiliation:
Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695
K. Bellur
Affiliation:
Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695
P. A. O'Neil
Affiliation:
Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695
A. Srivastava
Affiliation:
Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695
K. E. Violette
Affiliation:
Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695
M. C. Oztiirk
Affiliation:
Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695
C. M. Osburn
Affiliation:
Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695
N. A. Masnari
Affiliation:
Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695
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Abstract

In this paper we report the first NMOSFETs with elevated S/D selectively deposited by ultra high vacuum rapid thermal chemical vapor deposition (UHV-RTCVD). The deposition process included an in-situ vacuum prebake (750 °C for 10 sec) followed by selective epitaxial growth (SEG) at 800 °C. Si2H6 was used as the silicon gas source instead of the more commonly used SiH4 and SiH2Cl2 in order to achieve high growth rates at low pressure. To prevent nucleation from occurring on insulator surfaces during growth, an etching mechanism was introduced by the addition of Cl2. The gases included 100 sccm of 10% Si2H6 in H2 and 2 sccm of Cl2 at a process pressure of 24 mTorr. An epitaxial growth rate of 160 nm/min has been achieved. The final epi thickness was around 0.1 μm. The S/D junctions were formed via ion implantation into the epi. The subsequent RTA (10 sec at 950 °C) resulted in an effective junction depth about 75 nm beneath the starting Si substrate. Process and device simulations reveal the importance of maintaining a shallow LDD junction for deep submicron devices by using low temperature selective deposition. MOSFETs exhibit good subthreshold characteristics with subthreshold swing of 86 mV/dec at a drain bias of 2.5 V, and threshold variations due to charge sharing and drain-induced-barrierlowering (DIBL) were moderate for Leff down to 0.35 μm. The gate-induced junction leakage current is below 2 pA/μm at a bias of 2.5 V.

Type
Research Article
Copyright
Copyright © Materials Research Society 1996

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