Chemical Mechanical polishing (CMP) is a useful technique for achieving global planarization in the ICs. The CMP of oxide has been used and studied for decades. Only recently the technique has been employed for planarizing the interlayer dielectric (ILD) on the silicon devices circuits. The effect of such polishing on the performance of the ILD has been the concern. This paper examines the attempts on defining the damage caused by CMP and its effect on the electrical properties after polished SiO2 wafers. In this investigation the PECVD and thermal oxide films were polished in the colloidal silica slurry on IC 60 pad. The polished oxide were then studied using I-V and nuclear reaction technique. The results show a surface damage which extends to about 800 Å in the polished oxide. The changes occurring in the concentration of hydrogenous species at the surface of SiO2 as determined by nuclear reaction technique will also be presented. It is shown that due to CMP as-deposited CVD SiO2 films loose water from surface regions whereas well annealed or dry oxides gain water at the surface. The results will be discussed and mechanisms will be presented to explain electrical results.
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