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Surface States at LT GaAs-n+ GaAs Interfaces

Published online by Cambridge University Press:  25 February 2011

Ashlsh K. Verma ,
J. S. Smith  and
Eicke R. Weber
Ashlsh K. Verma
Affiliation:
Department of Electrical Engineering, University of California, Berkeley, CA 94720.
J. S. Smith
Affiliation:
Department of Electrical Engineering, University of California, Berkeley, CA 94720.
Eicke R. Weber
Affiliation:
Department of Material Science, University of California, Berkeley, CA 94720.
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Extract

GaAs grown using Molecular Beam Epitaxy at below normal substrate temperatures (∼ 220 °C) has found many potential applications in GaAs MESFET devices. These so-called Low Temperature (LT) layers were originally used between the MESFET substrate and active region to eliminate backgating effects.[1] More recently, LT layers have been incorporated into MESFET gate structures to improve gate breakdown characteristics.[2] [3] When used in this capacity, the quality of the LT GaAs - n+ GaAs interface becomes an important issue: a large number of traps at the interface will result in channel mobility degradation. Furthermore, it is desirable to develop a method by which the interface quality can be evaluated through simple electrical measurements.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 281: Symposium D – Semiconductor Heterostructures for Photonic and Electronic Applications , 1992 , 85
Copyright
Copyright © Materials Research Society 1993

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References

REFERENCES

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