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The Use of X-ray Topography to Map Mechanical, Thermomechanical and Wire-Bond Strain Fields in Packaged Integrated Circuits

Published online by Cambridge University Press:  10 February 2011

Patrick J. McNally ,
R. Rantamäki ,
John W. Curley ,
T. Tuomi ,
A. N. Danilewsky  and
P. A. F. Herbert
Patrick J. McNally
Affiliation:
Microelectronics Research Laboratory, Dublin City University, Dublin 9, Ireland.
R. Rantamäki
Affiliation:
Optoelectronics Laboratory, Helsinki University of Technology, Finland.
John W. Curley
Affiliation:
Microelectronics Research Laboratory, Dublin City University, Dublin 9, Ireland.
T. Tuomi
Affiliation:
Optoelectronics Laboratory, Helsinki University of Technology, Finland.
A. N. Danilewsky
Affiliation:
Kristallographisches Institut, Universität Freiburg, D-79104 Freiburg Germany.
P. A. F. Herbert
Affiliation:
Plasma Ireland Ltd., 22 Summerhill North, Cork, Ireland.
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Abstract

Thermal processing steps in the production of packaged integrated circuits can lead to thermomechanical stresses. Additionally, the process of bonding wires to contact pads can lead to strain fields attributable to these. Synchrotron x-ray topography has been applied to packaged EEPROM Si ICs in order to produce maps of the strain fields induced by such processing steps. This technique allows for depth-resolved mapping with resolutions currently in the region of 5–10 μm throughout the entire mapping volume.

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Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 505 , 1997 , 241
Copyright
Copyright © Materials Research Society 1998

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References

REFERENCES

[1]Slattery, O., Hayes, T., Lawton, W., Kelly, G., Lydon, C. and O'Mathuna, C., J. Materials Proc. Technol., 54 (1–4), 199 (1995).Google Scholar
[2]Amagai, M. and Kawasaki, E., Mat. Res. Soc. Symp. Proc., 338, 185 (1994).Google Scholar
[3]Leonhardt, D.A., Semiconductor International, 19 (5), 311 (1996).Google Scholar
[4]Pantaleon, R., Sanchez-Mendoza, J. and Mena, M., Proc. Electronic Components and Technology Conf., 1–4 May 1994, Washington, DC, USA, 733–740 (1994).Google Scholar
[5]Liu, S. and Mei, Y., IEEE Trans. Components, Packaging and Manuf. Technol. A, 18 (3), 634 (1995).Google Scholar
[6]Miura, H., Kitano, M., Nishimura, A. and Kawai, S., Proc. 1992 Joint ASME/JSME Conf. On Electronic Packaging, 9–12 April 1992, Milpitas, CA, USA, 2, 957 (1992)Google Scholar
[7]Yalamanchili, P., Christou, A., Martell, S. and Rust, C., IEEE Circuits and Devices Magazine, 10 (4), 36–41 (1994).Google Scholar
[8]Sauvage-Simkin, M. in Synchrotron Radiation Research, eds. Winick, H. and Doniach, S., pp. 179–204, Plenum (1982).Google Scholar
[9]Tuomi, T., Naukkarinen, K. and Rabe, P., phys. stat. sol. (a), 25, 93–106 (1974).Google Scholar
[10]Yao, G. D., Dudley, M. and Wu, J., J. X-Ray Sci. Technol., 2, 195 (1990).Google Scholar
[11]Miltat, J. and Dudley, M., J. Appl. Crystallogr., 13, 555 (1980).Google Scholar