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Noise measurements on single electron transistors using bias switching read-out

Published online by Cambridge University Press:  15 September 2000

P. J. Hakonen ,
M. Kiviranta ,
J. S. Penttilä  and
M. A. Paalanen
P. J. Hakonen*
Affiliation:
Low Temperature Laboratory, Helsinki University of Technology, PO Box 2200, 02015 Espoo HUT, Finland
M. Kiviranta
Affiliation:
VTT Automation, Measurement Technology, PO Box 1304, 02044 VTT, Finland
J. S. Penttilä
Affiliation:
Low Temperature Laboratory, Helsinki University of Technology, PO Box 2200, 02015 Espoo HUT, Finland
M. A. Paalanen
Affiliation:
Low Temperature Laboratory, Helsinki University of Technology, PO Box 2200, 02015 Espoo HUT, Finland
*
pjh@neuro.hut.fi
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Abstract

We present a simple bias reversal technique for single electron transistors (SET) to remove fluctuations of tunneling resistance from the read-out signal at low frequencies. The gain of the device is kept constant under bias reversal by using asymmetric junction capacitances. In our Al/AlOx/Al devices with 1.2 μm island size and 100 × 100 nm2 tunnel junctions, the noise at 10 Hz is $6 \times 10^{-4} e/\sqrt{\mathrm{Hz}}$, independent of the bias modulation.

Keywords

Type
Research Article
Information
The European Physical Journal - Applied Physics , Volume 11 , Issue 3 , September 2000 , pp. 227 - 229
Copyright
© EDP Sciences, 2000

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References

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The large difference in the capacitance of our planar gate structures is due to different substrates: small C g corresponds to a device on a 120-nm thick Si3N4 membrane while the other one was made on thermally oxidized silicon.
A simplified version of the Stanford SR570 current preamplifier.
Programs for SET calculations were provided by A.N. Korotkov.
A.N. Korotkov, Appl. Phys. Lett. 69, 2593 (1996).