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Threads and or-parallelism unified

Published online by Cambridge University Press:  09 July 2010

VíTOR SANTOS COSTA ,
INÊS DUTRA  and
RICARDO ROCHA
VíTOR SANTOS COSTA
Affiliation:
CRACS and INESC-Porto LA, Faculty of Sciences, University of Porto Rua do Campo Alegre, 1021/1055, 4169-007 Porto, Portugal (e-mail: vsc@dcc.fc.up.pt, ines@dcc.fc.up.pt, ricroc@dcc.fc.up.pt)
INÊS DUTRA
Affiliation:
CRACS and INESC-Porto LA, Faculty of Sciences, University of Porto Rua do Campo Alegre, 1021/1055, 4169-007 Porto, Portugal (e-mail: vsc@dcc.fc.up.pt, ines@dcc.fc.up.pt, ricroc@dcc.fc.up.pt)
RICARDO ROCHA
Affiliation:
CRACS and INESC-Porto LA, Faculty of Sciences, University of Porto Rua do Campo Alegre, 1021/1055, 4169-007 Porto, Portugal (e-mail: vsc@dcc.fc.up.pt, ines@dcc.fc.up.pt, ricroc@dcc.fc.up.pt)
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Abstract

One of the main advantages of Logic Programming (LP) is that it provides an excellent framework for the parallel execution of programs. In this work we investigate novel techniques to efficiently exploit parallelism from real-world applications in low cost multi-core architectures. To achieve these goals, we revive and redesign the YapOr system to exploit or-parallelism based on a multi-threaded implementation. Our new approach takes full advantage of the state-of-the-art fast and optimized YAP Prolog engine and shares the underlying execution environment, scheduler and most of the data structures used to support YapOr's model. Initial experiments with our new approach consistently achieve almost linear speedups for most of the applications, proving itself as a good alternative for exploiting implicit parallelism in the currently available low cost multi-core architectures.

Keywords

multi-threadingor-parallelismimplementation

Information

Type
Regular Papers
Information
Theory and Practice of Logic Programming , Volume 10 , Special Issue 4-6: 26th International Conference on Logic Programming , July 2010 , pp. 417 - 432
Copyright
Copyright © Cambridge University Press 2010

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