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On fundamental limits to glacier flow models: computational theory and implications

Published online by Cambridge University Press:  08 September 2017

David Bahr*
Affiliation:
Department of Physics and Computational Science, Regis University, Denver, Colorado 80221, USA E-mail: dbahr@regis.edu
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Abstract

No single flow model can simulate all possible glaciers and ice sheets without violating fundamental tenets of computational science. The root cause is not one of numerical sophistication, precision or accurate initial conditions. Instead, using flow and transport as data transmission, glaciers inadvertently function as information processors. This computational capability confers a level of complexity that inherently limits our ability to accurately and efficiently predict glacier flow and therefore, for example, to forecast those aspects of climate systems that depend on glaciers. In particular, even with considerable future advancements in glacier physics, computational theory shows that no dramatic improvements in numerical speed are likely when compared to today’s glacier models. Therefore, to increase speed and resolution, the next generation of climate and sea-level models must rely on simulations tailored to specific ice-sheet geometries rather than general-purpose glacier flow models. However, because glaciers process information, entirely new computation-theoretic advances in glaciology are possible, and concepts from information entropy may help to define new glacier scaling relationships and identify which geometries will be most problematic for modeling.

Information

Type
Research Article
Copyright
Copyright © International Glaciological Society 2009
Figure 0

Fig. 1. Aerial view of Columbia Glacier, 2005. Several branches of the glacier network are visible, flowing from the top right to the bottom left and terminating in the waters of Prince William Sound. The black stripes are formed from rock, which falls from cliffs and is then advected along the glacier. (Image courtesy of W.T. Pfeffer, Institute of Arctic and Alpine Research, University of Colorado.)

Figure 1

Fig. 2. Truth tables for logic gates. Each gate has one or two inputs whose values can be 0 or 1 as shown on the left (sometimes referred to as false = 0 and true = 1). The output of each gate is shown on the right. The output of a NAND gate is the same as an AND gate whose output is fed to a NOT gate. A variety of other gates can be specified by switching values at the outputs. However, all possible gates can be constructed by stringing together sequences of NAND gates (Mano and Ciletti, 2007). The text shows how to build AND gates from glacier confluences (with incoming branches 1 and 2) and NOT gates from sinuous curves in a glacier path. Together a glacier confluence and curve form a universal NAND gate.

Figure 2

Fig. 3. Logic gates are formed by particles moving along branches of a glacier and merging at a confluence (shown as the dashed line). Analogous to electrons moving along two wires that join into a single wire, the merging particles do not occupy the same physical space at the confluence. The particles may move laterally and even vertically by following plunging and emerging flow vectors, but the Boolean value assigned to each particle is given only by its x position relative to a hypothetical particle traveling at a uniform speed along an x axis (see text and Fig. 4). All particles that reach the confluence (dashed line) within a specified time interval are assigned Boolean values; if the majority of particles over that time interval are 0’s (or 1’s) then the logic gate’s output value is a 0 (or 1).

Figure 3

Fig. 4. Assigning Boolean values to particles on a glacier network. The two grids represent different times separated by an interval τ = 7. On each grid, part A shows a hypothetical reference particle moving along the x axis. Part B shows a stylized version of a confluence like that on Columbia Glacier in Figure 3. Part C shows a stylized section of a glacier that has a sinuous curve but no confluence. For convenience, assume each particle moves one unit L per time-step in the directions indicated by the network (in general, the velocities may vary). Each particle falls an even or an odd distance from the reference A (as measured along the x axis only) and represents a 0 or 1 respectively. In total, the left input of B is assigned value 1 because the majority of particles are 1’s. The right input of B has an equal distribution and is assigned a 1 because the leading particle is a 1 (see text). Over the time interval τ = 7, the particles in B have merged onto a single path, but each particle retains its unique identity (see Fig. 3). After merging, the majority of particles are odd and the output of the gate is a 1 (consistent with an AND gate). In C, the particle starts as a 1 but ends as a 0 due to the delay of one unit L caused by the sinuous curve. Therefore C represents a NOT gate.

Figure 4

Fig. 5. Regions of AND versus OR behavior. Consider a glacier confluence (as in Fig. 3 and Fig. 4 part B) where each input has n and m odd particles out of a total of N and M particles. The inputs represent 0 or 1 depending on whether or not the odd particles are in the minority or the majority. For the given inputs, the output of the intersection will behave as either an AND or an OR gate (or both). In particular, for any point in the parameter space, the output is 0 or 1 as indicated. In general, if an AND gate is desired (gray regions) then one-quarter of the parameter space inappropriately behaves as an OR gate (white regions). The line separating 0’s from 1’s is derived from n + m = (N + M)/2, the condition that separates a minority from a majority of odd particles at the output (an output of 0 versus 1). The Appendix proves that if we desire only AND gates, then some input arrangement of particles (n, m, N and M) exists so that only the gray shaded region of the parameter space is reached at every glacier confluence.

Figure 5

Fig. 6. Example of error-checking triplets. The original circuit in the first box contains two stylized NAND gates constructed from ANDs and NOTs. For all possible inputs I1, I2, I3 (i.e. particle arrangements), this circuit will give the correct answer only (3/4)2, or 9/16, of the time and must be error-checked. As shown, six additional outputs are required to check the original output O1. The second box shows the circuits used to error-check the upper NAND gate. If the triplet (I1, I2, I4) is (0, 1, 0) or (1, 0, 0), then the gate has failed. The third box shows the circuits and triplet (I4, I3, O1) used to error-check the lower NAND gate.