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Versatile UAV hardware platform for accelerating indoor aerial navigation research

Published online by Cambridge University Press:  25 March 2026

Kyriakos M. Deliparaschos*
Affiliation:
Electrical and Computer Engineering and Informatics Department, Cyprus University of Technology, Limassol, Cyprus
Xuefei Huang
Affiliation:
Electrical and Computer Engineering and Informatics Department, Cyprus University of Technology, Limassol, Cyprus
Michalis Neofytou
Affiliation:
NMN Systems LTD, Limassol, Cyprus Cyprus University of Technology: Technologiko Panepistemio Kyprou, Cyprus
Savvas G. Loizou
Affiliation:
Department of Mechanical Engineering and Materials Science and Engineering, Cyprus University of Technology, Limassol, Cyprus
Argyrios Zolotas
Affiliation:
Faculty of Engineering and Applied Sciences, Cranfield, United Kingdom
*
Corresponding author: Kyriakos M. Deliparaschos; Email: k.deliparaschos@cut.ac.cy
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Abstract

This study presents a bespoke hardware platform for indoor navigation, featuring a quadrotor equipped with an FZ3 card incorporating the AMD (formerly Xilinx) Zynq UltraScale+ ZU3EG MPSoC as the onboard computer. A core component of this platform is a field programmable gate array (FPGA) module specifically designed to efficiently compute Delaunay triangulations, enabling enhanced spatial awareness and real-time surface reconstruction. The onboard computer communicates with the flight controller, inertial measurement unit (IMU), ultra-wideband (UWB) localisation system, stereo camera, light detection and ranging (LiDAR) and ultrasonic sensors via robotic operating system (ROS) 2. The primary objective is to develop a cost-effective, modular unmanned aerial vehicle (UAV) system that can be adapted for a range of indoor navigation applications. The modular design supports different onboard computer platforms and sensor configurations, allowing researchers to easily customise the system for various experiments. By providing a practical framework for precise indoor navigation, this platform addresses the limitations of simulated, simplified laboratory setups, accelerating prototyping and supporting the deployment of UAVs in complex real-world environments. This work explores the UAV’s hardware architecture, the implementation of the Delaunay triangulation core on the FPGA system-on-chip (SoC), the ROS 2-based communication system and includes a detailed mass analysis and power estimation.

Information

Type
Research Article
Creative Commons
Creative Common License - CCCreative Common License - BY
This is an Open Access article, distributed under the terms of the Creative Commons Attribution licence (https://creativecommons.org/licenses/by/4.0/), which permits unrestricted re-use, distribution and reproduction, provided the original article is properly cited.
Copyright
© The Author(s), 2026. Published by Cambridge University Press on behalf of Royal Aeronautical Society
Figure 0

Figure 1. Quadrotor system architecture.

Figure 1

Figure 2. F450 quadrotor model with coordinate frame.

Figure 2

Figure 3. The Stanford Bunny model (left) has been reconstructed (right, comprising 397 points). For improved viewing clarity, the DT figure on the right has been post-processed and does not depict the convex hull of the surface points.

Figure 3

Algorithm 1: Incremental Delaunay Triangulation Algorithm

Figure 4

Table 1. Features of the FZ3 accelerator card

Figure 5

Figure 4. Block-level overview of the Zynq UltraScale+ SoC architecture and its subsystems. Adapted from Ref. (32).

Figure 6

Figure 5. DT core implementation on PL side.

Figure 7

Figure 6. DT core architecture.

Figure 8

Figure 7. ROS 2-based communication architecture.

Figure 9

Figure 8. Framework workflow process.

Figure 10

Figure 9. FPGA design module performance: latencies in terms of clock cycles and time (ns).

Figure 11

Table 2. Latency analysis of the DT core architecture

Figure 12

Figure 10. HDL model co-simulation.

Figure 13

Figure 11. Stanford Bunny, sampled at different numbers of points.

Figure 14

Figure 12. Comparison between software and FPGA core.

Figure 15

Table 3. Performance results (time in ms)

Figure 16

Table 4. Mass breakdown of the various UAV platform components

Figure 17

Table 5. Expected maximum power draw of the UAV components

Figure 18

Figure 13. Implementation of the multirotor UAV.