Wafer-level three-dimensional (3D) integration as an emerging architecture
for future chips offers high interconnect performance by reducing delays of
global interconnects and high functionality with heterogeneous integration
of materials, devices, and signals. Various 3D technology platforms have
been investigated, with different combinations of alternative alignment,
bonding, thinning and inter-wafer interconnection technologies. Precise
alignment on the wafer level is one of the key challenges affecting the
performance of the 3D interconnects. After a brief overview of the
wafer-level 3D technology platforms, this paper focuses on waferto-wafer
alignment fundamentals. Various alignment methods are reviewed. A higher
emphasis lies on the analysis of the alignment accuracy. In addition to the
alignment accuracy achieved prior to bonding, the impacts of wafer bonding
and subsequent wafer thinning will be discussed.