SoC examples

Sorin Voinigescu

doi:10.1017/CBO9781139021128.014

13 - SoC examples

Published online by Cambridge University Press: 05 March 2013

Sorin Voinigescu

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Sorin Voinigescu: Affiliation:
University of Toronto

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Summary

This chapter presents a possible design flow, along with biasing, isolation and layout strategies suitable for mm-wave SoCs. Competing transceiver architectures, self-test, and packaging approaches are reviewed next, followed by examples of mm-wave SoCs for a wide range of new applications.

What is a high-frequency SoC?

Although a precise definition is difficult to formulate, we define a high-frequency SoC as a single-chip radar, sensor, radio or wireline communication transmitter, receiver or transceiver that includes all high-frequency blocks, sometimes even the antennas, along with digital control and signal-processing circuitry.

Examples include:

2GHz cell-phone or 5GHz wireless LAN transceivers
40Gb/s or 100Gb/s SERDES
60GHz radio transceiver
77GHz automotive radar transceiver
W-, D-, and G-Band active and passive imagers.

DESIGN METHODOLOGY FOR HIGH-FREQUENCY SoCs

Most foundries have recently decided that the MOSFET and SiGe HBT compact models should capture the parasitic capacitance and resistance of only the first 1–2 metal layers, the minimum required for contacting all the device terminals. The rationale invoked is that this approach allows circuit designers more flexibility in the physical layout of transistors and of commonly encountered transistor groupings such as interdigitated differential pairs, interdigitated Gilbert cell quads, and latches. One (major) impediment is that, since most of the backend parasitics are not accounted for in schematic-level simulations, the burden is passed on to the designer to first lay out and then extract the parasitic impedance of the full wiring stack above the transistor in order to get an accurate simulation of circuit performance. This, in turn, creates a problem since, in most cases, the design starts with schematic-level simulations to find the optimal transistor size.

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Type: Chapter
Information: High-Frequency Integrated Circuits , pp. 803 - 850

DOI: https://doi.org/10.1017/CBO9781139021128.014 [Opens in a new window]

Publisher: Cambridge University Press

Print publication year: 2013

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References

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