1 - Introduction
3D Integration and Near-Field Coupling
Published online by Cambridge University Press: 17 September 2021
Summary
Chapter 1 starts by tracing the history of the computer, integrated circuit (IC), and connector in the last 60 years. In particular, it describes how the goal of IC development evolved from high-performance IC to low-power IC and interface, and then to high energy efficiency. This provides the background to help the reader understand current and future challenges faced by the IC and connector in addressing the diverging performance needs of various emerging applications. This in turn sets the stage for the introduction of 3D IC integration, which is evolving from low-cost wirebond to high-performance and high-density TSV-based solutions to offer More than Moore performance improvement. The challenges faced by 3D integration are then enumerated, and 2.5D integration and wireless interface technologies are presented as current and future solutions respectively. A brief overview of wireless technologies is then provided, followed by an explanation of why near-field coupling has been applied to develop two wireless interface technologies – ThruChip Interface (TCI) and Transmission Line Coupler (TLC). The chapter concludes with an overview of TCI and TLC and an elaboration of how they address respectively the challenges in 3D IC integration and connector performance scaling.
Keywords
Information
- Type
- Chapter
- Information
- Publisher: Cambridge University PressPrint publication year: 2021
References
Kuroda, T.. “Semiconductor industry in 2025,” Panel Discussion (presented but not published). 2010 IEEE International Solid-State Circuits Conference, Feb. 2010. Updated Nov. 2019.Google Scholar
Kuroda, T. and Sakurai, T.. (1995, Apr.). “Overview of low-power ULSI circuit techniques.” IEICE Transactions on Electronics. E78-C(4), pp. 334–344.Google Scholar
Kuroda, T.. “Will SOI ever become a mainstream technology?” Panel Discussion (presented but not published), 2002 IEEE International Electron Devices Meeting, Dec. 2002.Google Scholar
TE Connectivity Ltd. Retrieved on Jun. 11, 2019. Available: www.te.com/usa-en/products/brands/amp.html?tab=pgp-storyGoogle Scholar
SMK Corporation, “電線対基板圧着コネクタの動向 [Crimped connector trends],” in Japanese. Retrieved on Jun. 11, 2019. Available: www.smk.co.jp/products/connectors/technology/1002dempaCSbtow/Google Scholar
Process technology history – Intel. WikiChip. Retrieved on Jun. 11, 2019. Available: https://en.wikichip.org/wiki/intel/processGoogle Scholar
Japan Electronics and Information Technology Industries Association (JEITA). (2017, Mar.). “2026 年までの電子部品技術ロードマップ [Roadmap of electronic component technology up to year 2026].” In Japanese. Retrieved on Jun. 11, 2019. Available: www.jeita.or.jp/japanese/assets/pdf/letter/vol21/15.pdfGoogle Scholar
Kuroda, T.. (1999, Apr.). “ディープサブミクロン時代の半導体集積回路の技術課題とEDAへの期待 [Technological challenges of IC in the deep submicron age and expectations for EDA].” 情報処理学会論文誌 [IPSJ Journal], 40(4), pp. 1500–1506.Google Scholar
Kuroda, T.. (2007, Nov.). “システムLSIの低電力技術 [Low-power technology for system LSI].” 電子情報通信学会誌 [Journal of Institute of Electronics, Information and Communication Engineers], 90(11), pp. 977–981.Google Scholar
Suzuki, K., Mita, S., Fujita, T., Yamane, F., Sano, F., Chiba, A., Watanabe, Y., Matsuda, K., Maeda, T., and Kuroda, T.. “A 300MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS.” 1997 IEEE Custom Integrated Circuits Conference, pp. 587–590, May 1997.Google Scholar
Kuroda, T.. “Optimization and control of VDD and VTH for low-power, high-speed CMOS design.” 2002 IEEE/ACM International Conference on Computer-Aided Design, pp. 28–34, 2002.Google Scholar
Kuroda, T., Fujita, T., Mita, S., Nagamatsu, T., Yoshioka, S., Suzuki, K., Sano, F., Norishima, M., Murota, M., Kako, M., Kinugawa, M., Kakumu, M., and Sakurai, T.. (1996, Nov.). “A 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme.” IEEE Journal of Solid-State Circuits. 31(11), pp. 1770–1779.Google Scholar
Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Kuroda, T., and Furuyama, T.. (1998, Nov.). “A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme.” IEEE Journal of Solid-State Circuits. 33(11), pp. 1772–1780.Google Scholar
Fuketa, H., Yasufuku, T., Iida, S., Takamiya, M., Nomura, M., Shinohara, H., and Sakurai, T.. “Device-circuit interactions in extremely low voltage CMOS designs (invited).” 2011 IEEE International Electron Devices Meeting, pp. 559–562, Dec. 2011.Google Scholar
De, V.. “Energy efficient computing in nanoscale CMOS: Challenges and opportunities (plenary),” 2014 IEEE Asian Solid-State Circuits Conference, pp. 5–8, Nov. 2014.Google Scholar
Ishigaki, T., Tsuchiya, R., Morita, Y., Sugii, N., and Kimura, S.. (2010). “Ultralow-power LSI technology with silicon on thin buried oxide (SOTB) CMOSFET,” in Solid State Circuits Technology, Swart, J. W., Ed. Croatia: INTECH, 2010, ch. 7, pp. 145–156.Google Scholar
Topaloglu, R. O. and Wong, H.-S. P., Eds. (2015). Beyond-CMOS Technologies for Next Generation Computer Design. Cham, Switzerland: Springer.Google Scholar
Fant, K.. (2005). Logically Determined Design: Clockless System Design with NULL Convention Logic. Hoboken: Wiley-Interscience.Google Scholar
Maruyama, T., Hamada, M., and Kuorda, T.. (2018, Aug.). “Comparative performance analysis of dual-rail domino logic and CMOS logic under near-threshold operation,” IEEE International Midwest Symposium on Circuits and Systems, pp. 25–28.Google Scholar
Rowley, J. D.. (2018, Mar.). “Venture funding into AI and machine learning levels off as tech matures.” Retrieved on Jun. 12, 2019. Available: news.crunchbase.com/news/venture-funding-ai-machine-learning-levels-off-tech-matures/.Google Scholar
Tyson, M.. (2018, Jun.). “Intel 10nm density is 2.7× improved over its 14nm node.” Retrieved on Jun. 12, 2019. Available: https://hexus.net/tech/news/cpu/119699-intel-10nm-density-27x-improved-14nm-nodeGoogle Scholar
Hruska, J.. (2018, Jun.). “As chip design costs skyrocket, 3nm process node is in jeopardy.” Retrieved on Jun. 12, 2019. Available: www.extremetech.com/computing/272096-3nm-process-nodeGoogle Scholar
Manners, D.. (2014, Apr.). “EUV cost is $14bn and counting.” Retrieved on Jun. 12, 2019. Available: www.electronicsweekly.com/news/business/finance/euv-cost-14bn-counting-2014-04/Google Scholar
Moore, S.. (2018, Jan.). “EUV lithography finally ready for chip manufacturing.” Retrieved on Jun. 12, 2019. Available: https://spectrum.ieee.org/semiconductors/nanotechnology/euv-lithography-finally-ready-for-chip-manufacturingGoogle Scholar
Aochi, H., Katsumata, R., and Fukuzumi, Y.. (2011). “BiCS flash memory for realization of ultrahigh-density nonvolatile storage devices.” In Japanese. Toshiba Review. 66(9), pp. 16–19.Google Scholar
(2005, Oct.). “LSIは平面から立体へ チップを貫く伝送路で実現 [Shift from 2D to 3D LSI integration realized using through-chip interconnects].” In Japanese. Nikkei Electronics, (2005/10/10) pp. 82–91.Google Scholar
Yano, Y., Sugiyama, T., Ishihara, S., Fukui, Y., Juso, H., Miyata, K., Sota, Y., and Fujita, K.. “Three-dimensional very thin stacked packaging technology for SiP.” 52nd Electronic Components and Technology Conference, pp. 1329–1334, May 2002.Google Scholar
Matsudera, K. and Kawasaki, K.. (2016). “World’s first 16-die stacked NAND flash memory package fabricated using TSV technology.” Toshiba Review. 71(6), pp. 20–23.Google Scholar
Worwag, W. and Dory, T.. “Copper via plating in three dimensional interconnects.” 2007 Electronic Components and Technology Conference, pp. 842–846, May 2007.Google Scholar
James, D.. (2014). “3D ICs in the real world.” 25th Annual SEMI Advanced Semiconductor Manufacturing Conference, pp. 113–119.Google Scholar
Ezaki, T., Kondo, K., Ozaki, H., Sasaki, N., Yonernura, H., Kitano, M., Tanaka, S., and Hirayarna, T.. “A 160Gb/s interface design configuration for multichip LSI.” 2004 IEEE International Solid-State Circuits Conference, pp. 140–141, Feb. 2004.Google Scholar
Burns, J., McIlrath, L., Keast, C., Lewis, C., Loomis, A., Warner, K., and Wyatt, P.. “Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip.” 2001 IEEE International Solid-State Circuits Conference, pp. 268–269, Feb. 2001.Google Scholar
Kanda, K., Antono, D. D., Ishida, K., Kawaguchi, H., Kuroda, T., and Sakurai, T.. “1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme.” 2003 IEEE International Solid-State Circuits Conference, pp. 186–187, Feb. 2003.Google Scholar
Mizoguchi, D., Yusof, Y. B., Miura, N., Sakura, T., and Kuroda, T.. “A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS).” 2004 IEEE International Solid-State Circuits Conference, pp. 142–143, Feb. 2004.Google Scholar
Kumagai, K., Yang, C., Izumino, H., Narita, N., Shinjo, K., Iwashita, S., Nakaoka, Y., Kawamura, T., Komabashiri, H., Minato, T., Ambo, A., Suzuki, T., Liu, Z., Song, Y., Goto, S., Ikenaga, T., Mabuchi, Y., and Yoshida, K.. “System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV.” 2006 IEEE International Solid-State Circuits Conference, pp. 430–431, Feb. 2006.Google Scholar
Hopkins, D., Chow, A., Bosnyak, R., Coates, B., Ebergen, J., Fairbanks, S., Gainsley, J., Ho, R., Lexau, J., Liu, F., Ono, T., Schauer, J., Sutherland, I., and Drost, R.. “Circuit techniques to enable 430Gb/s/mm2 proximity communication.” 2007 IEEE International Solid-State Circuits Conference, pp. 368–369, Feb. 2007.Google Scholar
Gu, Q., Xu, Z., Ko, J., and Chang, M.-C. F.. “Two 10Gb/s/pin low-power interconnect methods for 3D ICs.” 2007 IEEE International Solid-State Circuits Conference, pp. 448–449, Feb. 2007.Google Scholar
Miura, N., Mizoguchi, D., Inoue, M., Tsuji, H., Sakurai, T., and Kuroda, T.. “A 195Gb/s 1.2W 3D-stacked inductive inter-chip wireless superconnect with transmit power control scheme.” 2005 IEEE International Solid-State Circuits Conference, pp. 264–265, Feb. 2005.Google Scholar
Miura, N., Mizoguchi, D., Inoue, M., Niitsu, K., Nakagawa, Y., Tago, M., Fukaishi, M., Sakurai, T., and Kuroda, T.. “A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link.” 2006 IEEE International Solid-State Circuits Conference, pp. 424–425, Feb. 2006.Google Scholar
Miura, N., Ishikuro, H., Sakurai, T., and Kuroda, T.. “A 0.14pJ/b inductive-coupling inter-chip data transceiver with digitally-controlled precise pulse shaping.” 2007 IEEE International Solid-State Circuits Conference, pp. 358–359, Feb. 2007.CrossRefGoogle Scholar
Miura, N., Kohama, Y., Sugimori, Y., Ishikuro, H., Sakurai, T., and Kuroda, T.. “An 11Gb/s inductive-coupling link with burst transmission.” 2008 IEEE International Solid-State Circuits Conference, pp. 298–299, Feb. 2008.Google Scholar
Denda, S.. (2015.). 半導体の高次元化技術 [Enabling Technology for Higher Dimensional Semiconductors], in Japanese. Japan: Tokyo Denki University Press.Google Scholar
Kim, J.. “The future of graphic and mobile memory for new applications.” 2016 IEEE Hot Chips 28 Symposium, Aug. 2016.Google Scholar
Karmarkar, A. P., Xu, X., and Moroz, V.. “Performance and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV).” IEEE International Reliability Physics Symposium, pp. 682–687, Apr. 2009.Google Scholar
Samal, S. K., Nayak, D., Ichihashi, M., Banna, S., and Lim, S. K.. “Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology.” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, pp. 1–2, 2016.Google Scholar
Bolsens, I.. (2011). “2.5D ICs: Just a stepping stone or a long term alternative to 3D.” Retrieved Aug. 8, 2019. Available: www.xilinx.com/publications/about/3-D_Architectures.pdf.Google Scholar
Madden, L., Wu, E., Kim, N., Banijamali, B., Abugharbieh, K., Ramalingam, S., and Wu, X.. “Advancing high performance heterogeneous integration through die stacking.” 2012 European Solid-State Circuit Conference, pp. 18–24, Sep. 2012.Google Scholar
Chen, W. C., Hu, C., Ting, K. C., Wei, V., Yu, T. H., Huang, S. Y., Chang, V.C.Y., Wang, C. T., Hou, S. Y., Wu, C. H., and Yu, D.. “Wafer level integration of an advanced logic-memory system through 2nd generation CoWoS® technology.” 2017 Symposium on VLSI Technology, pp. T54–T55, Jun. 2017.Google Scholar
Miura, N. and Kuroda, T.. (2008). 3次元実装のための低電力・広帯域誘導結合通信 [Low-power and wideband inductive-coupling communication for 3D integration]. In Japanese. エレクトロニクス実装学会誌 Journal of The Japan Institute of Electronics Packaging. 11(3), pp 174–181. Available: www.jstage.jst.go.jp/article/jiep1998/11/3/11_3_174/_pdf/-char/ja.Google Scholar
Ishikuro, H. and Kuroda, T.. (2010, Oct.). “Wireless proximity interfaces with a pulse-based inductive coupling technique.” IEEE Communications Magazine. 48(10), pp. 192–199.CrossRefGoogle Scholar
Kuroda, T.. “System integration in a package for cloud and edge.” 2017 IEEE Electron Devices Technology and Manufacturing Conference, pp. 42–43, Feb. 2017.Google Scholar
(2015). International Technology Roadmap for Semiconductors 2.0, 2015 Edition, Heterogeneous Integration. Available: www.dropbox.com/sh/3jfh5fq634b5yqu/AADYT8V2Nj5bX6C5q764kUg4a?dl=0&preview=2_2015+ITRS+2.0+Herogeneous+Integration.pdf.Google Scholar
Take, Y., Miura, N., and Kuroda, T.. “A 30 Gb/s/Link 2.2 Tb/s/mm2 inductively-coupled injection-locking CDR for high-speed DRAM interface.” 2010 IEEE Asian Solid-State Circuits Conference, pp. 81–84, Nov. 2010.Google Scholar
Miura, N., Shidei, T., Yuxiang, Y., Kawai, S., Takatsu, K., Kiyota, Y., Asano, Y., Kuroda, T.. “A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme.” 2010 Symposium on VLSI Circuits, pp. 201–202, Jun. 2010.CrossRefGoogle Scholar
Saito, M., Miura, N., and Kuroda, T.. “A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking.” 2010 IEEE International Solid-State Circuits Conference, pp. 440–441, Feb. 2010.Google Scholar
Saito, M., Sugimori, Y., Kohama, Y., Yoshida, Y., Miura, N., Ishikuro, H., Sakurai, T., and Kuroda, T.. (2010, Jan.). “2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND Flash memory stacking.” IEEE Journal of Solid-State Circuits. 45(1), pp. 134–141.Google Scholar
Niitsu, K., Shimazaki, Y., Sugimori, Y., Kohama, Y., Kasuga, K., Nonomura, I., Saen, M., Komatsu, S., Osada, K., Irie, N., Hattori, T., Hasegawa, A., and Kuroda, T. “An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.” 2009 IEEE International Solid-State Circuits Conference, pp. 480–481, Feb. 2009.Google Scholar
Osada, K., Saen, M., Okuma, Y., Niitsu, K., Shimazaki, Y., Sugimori, Y., Kohama, Y., Kasuga, K., Nonomura, I., Irie, N., Hattori, T., Hasegawa, A., and Kuroda, T.. “3D system integration of processor and multi-stacked SRAMs by using inductive-coupling links.” 2009 Symposium on VLSI Circuits, pp. 256–257, Jun. 2009.Google Scholar
Kosuge, A.. “伝送線路結合器を用いた高信頼非接触インタフェース [High reliability contactless interface using transmission line coupler],” in Japanese, Ph.D. dissertation, Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa Prefecture, Japan, 2016.Google Scholar
Meghelli, M., Rylov, S., Bulzacchelli, J., Rhee, W., Rylyakov, A., Ainspan, H., Parker, B., Beakes, M., Chung, A., Beukema, T., Pepeljugoski, P., Shan, L., Kwark, Y., Gowda, S., and Friedman, D.. “A 10Gb/s 5-Tap-DFE/4-Tap-FFE transceiver in 90nm CMOS.” 2006 IEEE International Solid-State Circuits Conference, pp. 213–214, Feb. 2006.Google Scholar
Shekhar, S., Jaussi, J. E., O’Mahony, F., Mansuri, M., and Casper, B.. “Design considerations for low-power receiver front-end in high-speed data links.” 2013 IEEE Custom Integrated Circuits Conference, pp. 1–8, Sep. 2013.Google Scholar
Musah, T., Jaussi, J. E., Balamurugan, G., Hyvonen, S., Hsueh, T.-C., Keskin, G., Shekhar, S., Kennedy, J., Sen, S., Inti, R., Mansuri, M., Leddige, M., Horine, B., Roberts, C., Mooney, R., and Casper, B.. (2014, Dec.). “A 4-32 Gb/s bidirectional link with 3-Tap FFE/6-Tap DFE and collaborative CDR in 22 nm CMOS.” IEEE Journal of Solid-State Circuits. 49(12), pp. 3079–3090.Google Scholar
Kosuge, A., Kadomoto, J., and Kuroda, T.. (2016, Jun.). “A 6 Gb/s 6 pJ/b 5 mm-distance non-contact interface for modular smartphones using two-fold transmission line coupler and high EMC tolerant pulse transceiver.” IEEE Journal of Solid-State Circuits. 51(6), pp. 1446–1456.Google Scholar
Kosuge, A., Hashiba, J., Kawajiri, T., Hasegawa, S., Shidei, T., Ishikuro, H., Kuroda, T., and Takeuchi, K.. “Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory.” 2015 Symposium on VLSI Circuits, pp. c218–c219, Jun. 2015.Google Scholar
Kosuge, A., Ishizuka, S., Taguchi, M., Ishikuro, H., and Kuroda, T.. (2015, Aug.). “Analysis and design of an 8.5-Gb/s/link multi-drop bus using energy-equipartitioned transmission line couplers.” IEEE Transactions on Circuits and Systems. 62(8), pp. 2122–2131.Google Scholar
Miura, N., Saito, M., Taguchi, M., and Kuroda, T.. (2013, Feb.). “A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×.” 2013 IEEE International Solid-State Circuits Conference, pp. 214–215.Google Scholar
Mizuhara, W., Shidei, T., Kosuge, A., Takeya, T., Miura, N., Taguchi, M., Ishikuro, H., and Kuroda, T.. “A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler.” 2013 IEEE International Solid-State Circuits Conference, pp. 200–201, Feb. 2013.Google Scholar
Kosuge, A., Ishizuka, S., Kadomoto, J., and Kuroda, T.. “A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver.” 2015 IEEE International Solid-State Circuits Conference, pp. 176–177, Feb. 2015.Google Scholar
Kosuge, A., Ishizuka, S., Liu, L., Okada, A., Taguchi, M., Ishikuro, H., and Kuroda, T.. “An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%.” 2014 IEEE International Solid-State Circuits Conference, pp. 496–497, Feb. 2014.Google Scholar
Kosuge, A., Ishizuka, S., Abe, M., Ichikawa, S., and Kuroda, T.. “A 6.5Gb/s shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%.” 2015 IEEE International Solid-State Circuits Conference, pp. 434–435, Feb. 2015.Google Scholar
Accessibility standard: Unknown
Why this information is here
This section outlines the accessibility features of this content - including support for screen readers, full keyboard navigation and high-contrast display options. This may not be relevant for you.Accessibility Information
Accessibility compliance for the HTML of this chapter is currently unknown
and may be updated in the future.