1.1.2.1 The “Big Bang”: Invention of the IC

One of the first general-purpose computers built was ENIAC (Figure 1.1), developed in the United States in 1945 and introduced in 1946. It was a gigantic piece of machine built with 100,000 components and weighed 27 tons. It consumed so much power – 150 kW – rumor has it that streetlights in the neighborhood dimmed when it was being operated. It had about 5,000,000 solder connections made by hand. Its heat-generating vacuum tubes had such poor reliability that a few of them broke and the system went down every day.

Figure 1.1 Programming ENIAC. Photo by US Army, public domain

The transistor, a more reliable replacement of the vacuum tube, was invented by William Shockley et al. in 1948, based on the groundwork laid by Bell Labs in the prior year. With much less heat generation and higher reliability, it enabled construction of much larger-scale systems. However, the increasing scale of computer systems led to the exponential growth in the number of interconnections between components and hence wiring complexity. It was such a challenging problem that it became known as the tyranny of numbers. The winning solution that emerged, among various proposed, was the IC.

The IC was invented by Jack Kilby and Robert Noyce in 1958–1959. At the time, Texas Instruments (TI) was working on the Micro-Module solution to the problem of the tyranny of numbers that enabled circuit components to be densely packed on a printed circuit board (PCB). Kilby, despite being a TI engineer, developed an alternate solution – the groundbreaking concept of a monolithic IC where all circuit elements are integrated on a single piece (mono) of semiconductor substrate (lithic). In the following year, Robert Noyce would develop the silicon implementation of the IC.

1.1.2.2 Spring: Explosive Growth through Scaling

Around the same time in December 1959, American physicist Richard Feynman delivered a lecture entitled “There’s Plenty of Room at the Bottom,” where he discussed scientific manipulation at the atomic level. This could be considered the start of nanotechnology research, a field that fueled the advance in IC technology and hence its explosive growth.

In 1965, Gordon Moore of Fairchild Semiconductor (and later of Intel Corporation) published a paper entitled “Cramming More Components into Integrated Circuits,” where he described the potential of the IC with its exponentially growing integration density. He observed that the number of components in an IC had doubled approximately every year, and speculated that such a growth rate would continue. This speculation would later become known as Moore’s law and set the collective target for the advance of the semiconductor industry.

Figure 1.2 illustrates how the dominant computing device has evolved as transistor count increases following Moore’s law, and the changing driving force behind the evolution. From around 1980 to 1995, transistor channel length shrank from 4 to 0.35 µm. Meanwhile, the number of transistors that can be integrated on an IC increased from 100,000 to 100,000,000. As a result of this increased chip-level integration, the computer evolved from being an engineering workstation to a personal computer (PC), and its adoption spread from being one per group to one per person. As the trend continued, the smartphone replaced the PC as the dominant computing device, the Internet of Things (IoT) became ubiquitous, and artificial intelligence (AI) computing finally entered into the mainstream.

Figure 1.2 Evolution of the integrated circuit [Reference Kuroda1].

In this manner, scaling fueled the explosive growth of the IC. Unfortunately, there was a trade-off with an undesirable consequence that lurked in the background as computational performance rose. Eventually, around 1995, it reared its ugly head in the form of a wall that threatened to stop further scaling.

1.1.2.3 Summer: The Power Wall

Around 1995, process scaling ran into a power wall. Scaling resulted in a continuous increase in power consumption, to the point that the IC released so much heat as to degrade its reliability, bringing further scaling to a halt. As an illustration, from 1980 to 1995, in 15 years, power consumption of an IC increased 1,000-fold. On a per-unit-area basis, an IC generated as much heat as an electric cooktop – you can fry an egg by powering an array of these chips under the fry pan! How did that happen?

In 1974, Robert Dennard, inventor of dynamic random-access memory (DRAM), formulated with his colleagues the scaling theory that describes an ideal scaling scenario where the electric field within the semiconductor device is kept constant. If you scale the supply voltage and physical dimensions of the device by the same factor, the electric field, which is a function of the ratio of voltage to distance, will remain constant. As a result, transistors whose operation is driven by manipulation of the electric field will perform the same way after scaling. Under this scaling scenario, power density would remain unchanged as well. Therefore, for the same chip size, power remains the same after scaling, and hence no heat generation or dissipation problems should arise (see the column “Constant electric field” in Table 1.1). Meanwhile, as the device gets smaller, more devices can be integrated in the same area, leading to lower manufacturing costs. Furthermore, the circuit resistor–capacitor (RC) time constant is reduced, resulting in higher operating speed. It is indeed a beautiful scenario that, if realized, would have no undesirable consequences.

Table 1.1. Transistor scaling scenarios

Scaling scenario		Constant electric field (ideal)	Constant voltage (actual, 1980–1995)
Scaling factor	Device size, x	½	½
	Gate oxide thickness, tox	½	½
	Voltage, V	½	1
Resultant change	Electric field, E	1	2
	Current, I $\propto$ V2/tox	½	2
	Resistance, R $\propto$ V/I	1	½
	Capacitance, C $\propto$ x2/tox	½	½
	RC delay, τ $\propto$ CR	½	¼
	Power, P $\propto$ CV2/ τ	¼	2
	Power density, p $\propto$ P/x2	1	8

Source: © 1995 IEICE, [Reference Kuroda and Sakurai2] table 1.

The reality was that scaling was implemented with no reduction in supply voltage. In other words, it was not a constant electric field but rather constant voltage scaling. In this case, the circuit ran even faster as RC delay was further reduced, IC computational performance went up further, and more chips were sold bringing in higher revenues. The flip side was a large increase in power (see the “Constant voltage” column in Table 1.1). Given that IC power consumption was small to begin with, its increase had initially only a secondary effect. Nevertheless, continuous scaling resulted in rapid increase in power consumption. Before long, it hit a painful limit. This power wall was therefore the result of an unintended side effect of nonideal scaling.

The power consumption increase with scaling was the result of the laws of physics. It is therefore not an easy problem to solve. Faced with the power wall, various schemes were devised to handle the extra power that came with performance increase. For instance, in power gating, circuit operations are diligently monitored. Whenever a circuit is not in use, its power is cut off. In another scheme, supply voltage is lowered whenever high circuit performance is not required. Such power-saving actions may sound obvious given that we practice similar power conservation in our daily life. But with hundreds of millions of transistors on a large-scale IC, uncovering waste is no simple task. For any waste we can find and eliminate, that much power can be exchanged for increased performance. In other words, “no gain in power efficiency, no gain in IC performance.” This is a trade-off IC development has continued to face to this day.

1.1.2.4 Fall: The Leakage Wall

Around 2005, scaling hit yet another wall – the leakage wall. Unlike the power wall, the leakage wall was not a result of the progression of scaling; rather, it was the consequence of scaling reaching its limits. As transistor channel length was scaled down to 100 nm, gate oxide thickness was reduced to 1.2 nm, about the thickness of 4 molecules. If the oxide layer were thinned further, it would be subject to quantum effects under which tunneling current would flow. But without proportional reduction in gate oxide thickness, further transistor scaling would weaken ability of the gate to properly turn off the channel, resulting in leakage current. It is analogous to a faucet not properly turned off, allowing water to drip.

The options for fixing the “leaky faucet” include changing materials, modifying the manufacturing process, or adjusting how the device is constructed, as shown in Figure 1.3. For example, dielectric materials with higher dielectric constant were introduced to increase electric field strength without reducing thickness. In parallel, development of a manufacturing process was started to introduce distortions in the silicon structure (strained silicon) to stretch the silicon atoms to boost mobility and hence current when the transistor is on, without increasing leakage when the transistor is off. Furthermore, transistor gate construction was transformed from being planar to three-dimensional, such as in a fin field-effect transistor (FinFET), in order to strengthen gate control of the channel.

Figure 1.3 Low leakage device technologies [Reference Kuroda3].

Nevertheless, all these are measures to provide temporary relief only; there are no good ways to counter quantum effects that result from the laws of physics.

1.1.2.5 Winter: The End of Scaling?

The cover of the April 2015 issue of IEEE Spectrum (Figure 1.4) depicts a flipped-over computer chip in the shape of a belly-up, dead bug, with the competing headlines of “Moore’s Law is dead” vs. “Long live Moore’s Law.” “Is Moore’s Law dead?” is the billion-dollar question faced by the IC industry: Is scaling, that has propelled the industry in the last half of a century, coming to an end? Has IC development entered its winter season?

Figure 1.4 IEEE Spectrum cover, April 2015.

© 2015 IEEE

Over the prior 40 years, the manufacturing cost per transistor had dropped by a factor of 4 million. However, as channel length shrank below 28 nm, this unit cost started to rise. The economic benefits from scaling finally started to disappear. IC manufacturing has become a privilege that only a few companies with deep pockets can afford due to the enormous investment required. Even the costs for making an R&D test chip have risen from only several hundred thousand dollars to several million dollars. Faced with such adverse economic reality, once thriving IC research in both the academia and industry is gradually losing momentum.

1.1.2.6 The Second Spring

Nonetheless, innovation is not slowing; it is only taking a different form. Innovation in the semiconductor industry over the last 60 years has been mainly driven by Moore’s law in process scaling that has fueled an exponential proliferation in IC quantity and made it ubiquitous in our society. With the slowing or even ending of scaling, innovation is shifting to enhancing quality, in terms of how we apply IC technology in various innovative ways to enrich our life. The excitement in dramatically improving the price performance of an IC has been replaced by excitement in research and development of novel applications, including automated driving, artificial intelligence, big data, and IoT. Each of these areas is exploring different innovative ways to realize the potential provided by the performance achieved in scaling – IC’s first act. After experiencing the excitement of achieving a 100 million-fold improvement in the price performance of a computer, we are witnessing the opening of the curtain on IC’s second act, where advance in IC technology enters its second spring to deliver enrichment across various facets of our life.

1.1.3.1 The Solderless Connection

The solderless electrical connection was invented by American engineer Uncas A. Whitaker in 1941 [4]. Known as a crimped termination, it is a connection formed by inserting open wires on one end into a small metal tube with a ring on the other end, and pressing the ring against the wires using a specialized tool (Figure 1.5). Compared to a rigid, soldered connection, this revolutionary technology delivers a much faster way to make and break a connection in a smaller space. Furthermore, it offers higher reliability in the face of shock and vibration. Consequently, when the United States entered World War II, the technology was widely adopted in military applications since it maintained electrical connections even under harsh operating conditions. Furthermore, it significantly increased the speed of equipment repair, including that of fighter jets on aircraft carriers, which was a critical advantage in wartime. After the war ended, the application of crimped termination was extended to commercial applications, especially those that required operation in harsh environment, including automotive and appliances, such as power tools for the homebuilding boom that ensued after the war.

Figure 1.5 A crimped termination.

© 2010 SMK Corporation [5]

The solderless electrical connection opened up the possibility for an easily breakable connection and hence the idea of an electronic connector, which enabled modularization and flexible selection of different combinations of modules in building a large-scale electronic system, resulting in flexibility, expandability, and scalability. System assembly can be done by users in the field, and it is easy to replace or upgrade part of the system. Consequently, it represented an advance that is parallel to the IC in solving the connection problem of large-scale systems.

1.1.3.2 Recent Challenges for the Connector

The introduction of the iPhone in 2007 set in motion the rapid shift from the PC to the smartphone as the dominant form of electronic and computing system. Even the first-generation iPhone represented an order-of-magnitude shrink in form factor compared to the PC. The subsequent exponential growth in functionality and performance of the smartphone with continuous, albeit incremental, shrink in form factor in the last decade only added to the pressure to continuously shrink both the footprint and height of the components within. Nevertheless, scaling of connector dimensions is not keeping pace with that of the IC. This is illustrated by the historic trend in the scaling of flexible printed circuit (FPC) connector pitch. Because of its flexibility, low profile, and small dimensions, FPC and its connector are commonly used in mobile devices. From 1996 to 2004, FPC connector pitch scaled by roughly 0.4× and its height by roughly 0.25× in eight years, corresponding to average scaling of 0.89× and 0.84× per year, respectively (Figure 1.6). By contrast, around the same time from 1995 to 2003, Intel process migrated from 350 to 90 nm, scaling gate length from 350 to 50 nm, or 0.14× in eight years [6]. More recently, based on the roadmap published by the Japan Electronics and Information Technology Industries Association (JEITA), mainstream pitch of FPC-to-PCB connectors used in small form-factor devices is projected to shift from 0.3–0.4 mm in 2016 to 0.2–0.3 mm in 2026 (Figure 1.7), which translates to total scaling of 0.714× over 10 years, and a modest average scaling of 0.967× per year. This represents a rapid deceleration in the scaling of FPC connector pitch.

Figure 1.6 FPC connector dimensions scaling, 1996–2004.

© 2010 SMK Corporation [5]

Figure 1.7 FPC connector pitch roadmap, 2016–2026.

© 2017 JEITA [7]

The challenges in scaling connector dimensions are not surprising given the mechanical processes required in manufacturing connectors. Furthermore, it is difficult to significantly scale the dimensions of the connector housing that is needed to provide mechanical stability to ensure a reliable connection, especially when it is subject to shock and vibration, such as in an automotive or space application. This is on top of the challenge in maintaining signal integrity as the data rates of signals passing through connectors rise rapidly. The time is ripe for another revolutionary connector technology to enable a leap in miniaturization and performance of electronic systems.

1.3.4.1 Nature of a TSV

Since electronic circuits are formed on the top surface of an IC, the straightforward way to connect to them is from the front side. Therefore, the natural way to stack more than two dice over each other is to stack all of them facing up and connect the top surface of individual dices to a common point to create interconnections, which is how it is done in a conventional wirebond stack. To enable a drastically different integration scheme, the die must be additionally processed in such a way as to enable its electronic circuits to be connected from the back side as well. Such is the concept of a TSV. It is an electrical connection that traverses the silicon substrate, thereby enabling connection to active circuits of the chip from its back side as well.

Figure 1.30 depicts the basic structure of a TSV fabricated using one of two commonly employed processes known as a via-middle process [Reference Denda42]. It connects the metal layers on the front side of the die to its back side. A microbump on each of the front and back sides allows the die to connect with an adjacent die above and below respectively. While the die in a single-chip package is generally 200–500 µm thick, for TSV 3D integration it is thinned to about 50 µm. A thinner die helps to keep the stack height low, even if many of them are stacked. But more importantly, it helps to keep the TSV short and hence its diameter small, while maintaining a certain via aspect ratio for manufacturability. A shorter TSV in turn results in a shorter fabrication time. A 50 µm die thickness results in a via diameter between 3 µm and 20 µm, with 5 µm being a typical value. The via wall consist of a SiO₂ insulating layer, a barrier layer that is, for example, made of tantalum (Ta), titanium oxide (TiO₂), or titanium nitride (TiN) to prevent copper from diffusing into the silicon substrate, as well as a copper seed layer. The copper seed layer serves as an electrode for plating to fill the via with copper, thereby completing the electrical connection from the front to back side of the die. Even with this simplified picture, it is clear that the structure of TSV consists of multiple structural components made of different materials. This has implications in processing complexity as well as yield and reliability due to thermomechanical stresses.

Figure 1.30 Structure of a TSV.

Reproduced by permission from Sei-ichi Denda, 半導体の高次元化技術 [Enabling Technology for Higher Dimensional Semiconductors], Japan: Tokyo Denki University Press, 2015. © Denda Sei-ichi 2015

The via-middle process is so named because the TSV formation occurs in the middle of the IC fabrication process, after the front end of line (FEOL) process to create the transistors, but before the back end of line (BEOL) process to form the metal layers. A second common process known as via-last creates the TSVs at the end of the IC fabrication process, after wafer thinning and bump formation. Figure 1.31 depicts where the TSV formation occurs within the IC fabrication flow, including the temperature profiles for each of the fabrication steps. The two TSV processes are different not only because of the different positions within the IC fabrication process flow, but also because of the very different process temperature profiles they are exposed to, resulting in different process complexities and cost and yield equations. Furthermore, for outsourced manufacturing, while the via-middle TSV process falls naturally within the flow of the foundry, the via-last process may occur either at the foundry or outsourced semiconductor assembly and test (OSAT) vendor. As a result, the choice of the TSV fabrication process has supply chain implications as well.

Figure 1.31 TSV formation within the IC fabrication process flow.

Reproduced by permission from Sei-ichi Denda, 半導体の高次元化技術 [Enabling Technology for Higher Dimensional Semiconductors], Japan: Tokyo Denki University Press, 2015. © 2015 Denda Sei-ichi

Figure 1.32 contrasts the use of TSV versus wirebond in 3D IC integration. The following key differences can be observed:

• TSV enables a smaller form factor: the wirebond stack requires additional area and height to accommodate the wire loops as well as bond pads on the package substrate. Besides, while the example in the figure uses 90 degree rotation of every other die to create clearance for the wire loops, when the dice are square and of the same size, spacers must be inserted between adjacent dice to create such clearance, which increases the stack height further.

• TSV enables more robust interconnection: the visual comparison in Figure 1.32 illustrates the contrast in interconnection complexity between the two solutions. While the interconnects in the TSV stack are short and tucked away, those in the wirebond stack are long and susceptible to mechanical force that can tangle them and cause electrical shorts.

• TSV enables a larger number of dice to be stacked: in the wirebond stack, the number of wires and their maximum length increase with the number of dice. Therefore, the maximum number of dice in the stack is limited by manufacturability and electrical requirements. Longer wires are more susceptible to sweeping force that can cause electrical shorts. Furthermore, longer wires have higher inductance that can lead to unacceptably large power supply noise and signal degradation, especially at high frequency.

• The TSV stack enables a higher interconnect density: while both TSV and wirebond pitch are on the order of 50 µm, TSVs are placed across the surface of the die while wirebonds are limited to its perimeter. Consequently, TSV increases interconnect density in a quadratic manner.

TSV is therefore an advanced technology offering a small form factor, robust, high-capacity stacking, and high interconnect density solution for 3D IC integration.

Figure 1.32 3D IC integration technology comparison: wirebond vs. TSV.

Reproduced by permission from Sei-ichi Denda, 半導体の高次元化技術 [Enabling Technology for Higher Dimensional Semiconductors], Japan: Tokyo Denki University Press, 2015. © 2015 Denda Sei-ichi

1.3.4.2 TSV for Wired IC Integration

The first industrywide effort to commercialize the application of TSV to wired 3D IC integration was driven by the Joint Electron Device Engineering Council (JEDEC) through its release of the Wide I/O specification in 2011. At the time, the mobile DRAM industry was looking for a solution to deliver a quantum leap in energy efficiency. The transition from the first- to second-generation low-power DRAM technology, LPDDR to LPDDR2, achieved an almost 50% reduction in I/O energy per bit in conjunction with a doubling of bandwidth, resulting in the same total power. However, the next transition achieved only another 35% reduction in energy per bit while the bandwidth again doubled, resulting in a 31% increase in total power. This is summarized in Table 1.4, which is based on data published in [Reference Denda42] and [Reference Kim43]. The continuous increase in data rate demanded by the industry was anticipated to make improvement in energy efficiency more and more difficult as LPDDR evolves. In particular, for the memory interface, higher data rates exacerbate signal integrity problems, including signal reflection, ISI, and crosstalk. Furthermore, skew in delay across LPDDR’s parallel data bus becomes a larger and larger percentage of bit time, especially as the bus width increases to achieve higher bandwidth. Meanwhile, a higher-frequency clock is harder to generate and distribute due to higher jitter, higher sensitivity to noise, and higher attenuation. All these problems require architectural and circuit improvements to solve, such as the use of equalization circuits, transmission line terminations, signal phase alignment circuits, phase locked loop (PLL), delay locked loop (DLL), on-chip power supply bypassing, and insertion of clock buffers that lead to increased power. As a result, the Wide I/O solution was proposed to take low-power memory development in a different direction to enable continuous bandwidth scaling while drastically improving energy efficiency.

Figure 1.33 depicts the construction of a Wide I/O memory system. It consists of one or more Wide I/O DRAM dice stacked on top of a processor die. The 3D die stack is interconnected with TSVs and microbumps, while the bottom processor die is flip-chip attached to the package substrate.

Figure 1.33 Construction of a Wide I/O memory system.

As the name suggests, Wide I/O adopts a very wide data bus to achieve high bandwidth while keeping the data rate and hence I/O power low. Despite running at ¼ the data rate, it delivers four times the bandwidth of LPDDR2. This is made possible by the use of TSV to enable the 512-bit wide data bus, which is 16 times that of LPDDR2. The use of TSV instead of the conventional PCB interconnect results in drastic reduction in both the interconnect area (5 µm TSV diameter vs. 100 µm PCB trace width) and length (50 µm TSV length vs. tens of mm of PCB trace length), thereby avoiding an order-of-magnitude increase in interface area while significantly reducing interconnect capacitance and transmission line effects. Furthermore, since the interface bypasses the package, the bus width is not limited by the pin count and cost of the package. As a result of the lower data rate and simpler interconnects, the energy per bit is reduced by an order of magnitude while bandwidth is more than tripled compared to LPDDR2 (Table 1.4).

1.3.4.3 2.5D IC Integration Using TSV

Despite the promise of dramatically improved energy efficiency, Wide I/O (both versions 1 and 2 released in 2011 and 2014 respectively) was not able to replace LPDDR as the low-power memory solution for mobile applications. After the release of the Wide I/O specification, LPDDR continued to evolve from LPDDR3 in 2012 to LPDDR5 in 2019, doubling the data rate in every generation, as shown in Figure 1.34 based on [Reference Kim43]. Meanwhile, energy efficiency improved by about 35% in every generation. This is not sufficient to fully offset the increase in power due to doubling of the data rate, so total memory I/O power goes up at maximum bandwidth. Nevertheless, the industry has so far decided to stay with this evolutionary path, due to challenges in applying TSV to 3D integration of heterogeneous dice.

Figure 1.34 Evolution of LPDDR bandwidth and energy efficiency.

The challenges in applying TSV to 3D integration of heterogeneous dice include added manufacturing cost, yield loss, thermomechanical reliability problems, and device performance degradation. The added manufacturing cost is the result of both added processing for TSV formation and die area overhead. Meanwhile, the complexity of the TSV structure and the multitude of materials used that have diverse coefficients of thermal expansion (CTEs) lead to creation of thermomechanical stresses when the die stack is subject to thermal cycling during both manufacturing and normal operation. Such stresses result in lower manufacturing yield, lower reliability, and semiconductor device performance degradation [Reference Karmarkar, Xu and Moroz44]. Furthermore, thermomechanical stress also occurs at the flip-chip bump interface between the bottom die in the stack and the package substrate below, due to CTE mismatch between silicon and the package substrate material, such as epoxy resin. Such stress exists in single-die packages as well. But the much thinner die in a 3D stack means it is more susceptible to warpage.

There are solutions to overcome some of these challenges, such as adding redundant TSVs and enlarging the TSV keep-out zone to keep active circuits away. But such solutions increase the already large area overhead. Figure 1.35 depicts a relative size comparison between TSVs and NAND gates. The study in [Reference Samal, Nayak, Ichihashi, Banna and Lim45] from 2016 estimated a die area overhead of almost 40% for a TSV diameter of 5 µm in a 14 nm FinFET process, while noting that practical TSV diameters could be up to 10 µm large.

Figure 1.35 Relative size comparison: TSV vs. NAND gate.

© 2016 IEEE. Reprinted, with permission, from [Reference Samal, Nayak, Ichihashi, Banna and Lim45]

One additional challenge for TSV 3D integration of heterogeneous dice arises when a high-power chip is placed toward the bottom of the stack, which is the case with Wide I/O, where the processor chip sits at the bottom. In this case, heat removal from the high-power chip can be a challenge even if there is a heat sink at the top, especially if there are many chips in the stack.

To alleviate these problems, an intermediate solution known as 2.5D IC integration has emerged that has achieved commercial success especially in the high-end FPGA and graphics processing unit (GPU) markets.

Figure 1.36 depicts the cross section of the first 2.5D integrated FPGA commercial product announced by Xilinx in late 2011 [Reference Bolsens46]. It illustrates the basic construction of a 2.5D IC using TSV. First, the ICs are not stacked and hence have no TSVs. This facilitates heat removal from the individual ICs and eliminates IC manufacturing and reliability problems related to the use of TSV. Second, there is a passive silicon interposer inserted between the ICs and package substrate. The interposer serves the sole purpose of interconnecting the ICs and the package substrate and hence contains no active circuits. Interchip connections consist of microbumps and metal traces only without using TSVs. TSVs in the interposer are only used for power, ground, and external I/Os. Consequently, the TSV density is much lower than in 3D IC integration. As a result, the interposer can be fabricated in a lower-performance, more mature, and hence less expensive process. Furthermore, since the use of TSV is limited to the passive interposer, there is no TSV-induced device performance degradation.

Figure 1.36 Cross section of a 2.5D integrated FPGA.

© 2012 IEEE. Reprinted, with permission, from [Reference Madden, Wu, Kim, Banijamali, Abugharbieh, Ramalingam and Wu47]

Figure 1.36 shows an example of homogeneous 2.5D integration where all the chips are of the same type. The same technology can be applied to integration of heterogeneous chips. For instance, in Virtex-7 HT, which is also introduced in [Reference Bolsens46], three FPGA chips are integrated with two 28G SerDes transceiver chips in a 2.5D package. Furthermore, 2.5D can be combined with 3D integration where one of the chips mounted on the silicon interposer is a 3D integrated IC. A representative example is high bandwidth memory (HBM), which is introduced later in this section.

As elaborated in [Reference Bolsens46], compared to 3D, 2.5D integration represents an evolutionary solution in terms of design flow, test, thermal, and reliability. Furthermore, a 2.5D integrated FPGA offers high logic cell capacity at much lower power. As an illustration, the Virtex-7 2000T FPGA from Xilinx is a homogeneous 2.5D integration of four identical 28 nm FPGA chips on top of a 65 nm silicon interposer. It contains a total of 2 million logic cells and about 10,000 connections between adjacent chips and consumes 19 W of power. Using conventional FPGAs, four individually packaged chips will be required to match the capacity, while consuming almost six times the power, with 28.6% consumed by the interconnections.

Without vertically stacking the ICs, 2.5D integration requires a larger area than 3D. But it offers similar interconnection density as 3D integration, as well as shorter interconnections and higher IC packing density and hence a smaller footprint than 2D integration, while overcoming some key challenges faced by 3D integration. The pros and cons of 2.5D integration compared to 2 and 3D are summarized in Table 1.5.

Given the smaller footprint, 3D is still the preferred solution over 2.5D when many dice need to be integrated, and when the application is less cost sensitive. A good example can be found in high-end GPU systems that have adopted the HBM DRAM solution to meet their large memory capacity and high-speed requirements. HBM utilizes a combination of 2.5D and 3D integration to deliver the highest memory performance. HBM DRAM is a 3D stack of DRAM core chips on top of a logic chip. This memory stack is then placed side by side with a high-performance processor on a passive silicon interposer to form a 2.5D integrated memory system. It thus combines the best of both worlds. Three-dimensional integration allows the DRAM footprint to remain small while providing large capacity. Meanwhile, 2.5D integration of the processor keeps TSVs out of the large and expensive die of the system, while enabling effective removal of the large amount of heat it generates.

Figure 1.37 shows both a conceptual drawing and an optical image of the cross section of an HBM solution from [Reference Chen, Hu, Ting, Wei, Yu, Huang, Chang, Wang, Hou, Wu and Yu48]. The optical image illustrates the relative dimensions of the different parts of the memory system. Note that the use of an eight-stack HBM memory component incurs no height penalty since it stays within the height of the SoC. However, the interposer does add to the overall thickness of the package even though it is relatively thin.

Figure 1.37 Cross section of an HBM memory subsystem.

© 2017 IEEE. Reprinted, with permission, from [Reference Chen, Hu, Ting, Wei, Yu, Huang, Chang, Wang, Hou, Wu and Yu48]

1.3.4.4 Wireless 3D Integration

Wireless communication, as opposed to wired communication, does not require physical contact, e.g., by the use of a wire, to establish the communication channel. As any user of WiFi knows, wireless communication frees you from being tethered and hence offers you great mobility and convenience. However, since the receiver can be anywhere within the communication range, the transmitted signal must likewise be available everywhere. As a result, wireless communication is generally higher cost and offers lower bandwidth (throughput) than wired communication. By contrast, due to its very short communication distance of <100 µm, wireless 3D IC integration can be optimized to compete with its wired counterpart in cost and performance, while offering other benefits.

First, the connection terminals in the form of either metal pads or inductive coils for wireless integration are manufactured as part of the standard IC metal layer fabrication process. As a result, there is minimal added processing cost. By contrast, TSVs require complicated mechanical and wafer-level processing, adding significant manufacturing cost. Second, since wireless integration uses AC coupling, it can be applied to chips supplied with different voltage levels without any level shifters. Third, because there is no physical connection, wirelessly integrated chips are detachable – it is as easy to disconnect as it is to connect them together. Likewise, individual chips can easily be wirelessly connected to and disconnected from probe cards, making them easy to test and without concern for damages that a physically connected probe can inflict.

Performance of wireless integration in terms of communication data rate and reliability, power consumption, and chip area can also be optimized to rival that of wired integration, for three reasons. First, unlike WiFi, the very short communication distance makes it possible to create large capacitive and inductive coupling coefficients. As a result, high communication reliability can be achieved without consuming a lot of power. Second, since the connection terminals of the integrated chips do not require a DC path to the external world, they can be insulated to avoid electrostatic discharge (ESD) so as to eliminate ESD protection circuits, thereby reducing capacitive loading on the interconnection. This enables both high data rate and low power consumption. Circuit area is reduced as well. Third, in the case of inductive coupling, since the magnetic field can penetrate through circuits on the silicon substrate, the inductive coils can be placed above active circuits with no keep-out area. (Keep-out area is, however, needed to suppress crosstalk to sensitive circuits.) Consequently, die area overhead is small. Contrast this with the use of TSVs, where each via requires a keep-out area, thus adding significant area overhead, especially when they are numbered in the thousands. To experimentally confirm these and other merits of the inductive coupling solution and to advance its development, an inductively coupled wireless interface was prototyped in several test chips between 2006 and 2008 (Figure 1.38).

Figure 1.38 Inductive coupling interface test chips from 2006–2008.

© 2008 The Japan Institute of Electronics Packaging. Reprinted, with permission, from [Reference Miura and Kuroda49]

Figure 1.39 depicts the schematics of the transmitter and receiver circuits, and simulated and measured waveforms from an inductive coupling interface fabricated in a 180 nm CMOS process in 2006 (top-left of Figure 1.38 and [Reference Miura, Mizoguchi, Inoue, Niitsu, Nakagawa, Tago, Fukaishi, Sakurai and Kuroda39]). A data rate of 1 Gbps at a bit error rate (BER) <10^–13 was achieved, delivering reliable communication comparable to that of a wired interface. To minimize chip area, the inductive coils were placed above the transmitter and receiver circuits. Yet, no appreciable degradation in communication reliability was detected. Furthermore, by implementing a four-phase time-multiplexing scheme to skew the timing of data switching in adjacent communication channels (interconnections), total crosstalk from neighboring channels was significantly reduced. This enabled operating 1,024 parallel channels at a 30 µm pitch simultaneously at a per-channel data rate of 1 Gbps at BER <10^–13, resulting in a total interface throughput of 1 Tb/s.

Figure 1.39 Inductive coupling test chip, 2006.

© 2008 The Japan Institute of Electronics Packaging. Reprinted, with permission, from [Reference Miura and Kuroda49]

Figure 1.40 compares the test interface from 2006 with alternate solutions from around the same time frame, in both total channel throughput and area/throughput, confirming the merits of the inductive coupling solution.

Figure 1.40 Benchmarking the 2006 inductive coupling test chip.

© 2008 The Japan Institute of Electronics Packaging. Reprinted, with permission, from [Reference Miura and Kuroda49]

The inductive coupling interface was further refined in a test chip in 2007 (middle of Figure 1.38 and [Reference Miura, Ishikuro, Sakurai and Kuroda40]) that achieved an energy efficiency comparable to that of wired communication. The energy efficiency of the 2006 test chip interface was dominated by the transmitter circuits, which consumed 2.2 pJ/b out of a total energy consumption of 2.8 pJ/b. By optimizing the shape of the transmitted pulse and reducing its width, in addition to migrating to a 90 nm process and reducing V_DD, the (transmitter + receiver) energy consumption was reduced by a factor of 1/20 to achieve 0.14 pJ/b, making it comparable to alternate wired solutions (Figure 1.41, [Reference Miura, Ishikuro, Sakurai and Kuroda40]).

Figure 1.41 Inductive coupling test chip, 2007.

© 2008 The Japan Institute of Electronics Packaging. Reprinted, with permission, from [Reference Miura and Kuroda49]

1.3.4.5 Inductive vs. Capacitive Coupling for 3D Integration

The key advantage of inductive coupling over capacitive coupling for 3D IC integration is twofold. First, signal loss through silicon substrate is small. While capacitive coupling relies on the vertical electric field between the two coupled terminals, inductive coupling utilizes the magnetic field linking the two terminals instead. Figure 1.42 depicts the simulated S₂₁ of the communication channel as a function of substrate resistivity when the substrate is in the transmission path, comparing inductive against capacitive coupling. S₂₁, which is defined as the ratio of output to input signal, is a parameter that quantifies signal transmission efficiency in the frequency domain. The results reveal that electric field is significantly more susceptible to loss to substrate resistivity than the magnetic field used in inductive coupling. When resistivity reaches around the 1~0.1 Ωcm value of p+ Si, capacitive coupling suffers a dramatic increase in loss. As a result, capacitive coupling cannot be used to communicate through a silicon substrate effectively. Instead, it is confined to face-to-face IC integration. The magnetic field does suffer loss due to eddy current induced in the substrate. However, the loss is small enough that the magnetic field can effectively penetrate p+ Si substrate, making it possible to apply inductive coupling to both face-up and back-to-back chip stacking.

Figure 1.42 Simulated S₂₁ dependency on substrate resistivity.

© 2008 The Japan Institute of Electronics Packaging. Reprinted, with permission, from [Reference Miura and Kuroda49]

A second advantage of inductive over capacitive coupling is its support for a longer communication distance. The equations defining the coupling and the transceiver circuits are compared in Figure 1.43. The voltage of the received signal through capacitive coupling is defined by the following equation:

$V_R=\frac{V_T{C}_C}{C_C+C_{\mathit{SUB}}},$(1.6)

where V_T is the transmitted voltage, C_C the capacitance between the coupled terminals, and C_SUB the capacitance between the receiver terminal and the underlying substrate (Figure 1.43a). As the communication distance and hence the distance between the coupled terminals increases, C_C and hence V_R decreases. This loss in V_R cannot be compensated by increasing the area of the coupled terminals since larger area increases both C_C and C_SUB proportionally. By contrast, the voltage of the received signal through inductive coupling is defined by the following equation:

$V_R=M\frac{\mathrm{d}{I}_T}{\mathrm{d}t},$(1.7)

where I_T is the transmitted current and M the mutual inductance between the coupled terminals (Figure 1.43b). The received voltage is proportional to M, which can be increased by increasing the area of the coupled coils. Therefore, within practical limits, longer communication distance can be supported by enlarging the inductive coils.

Figure 1.43 Mechanism of capacitive and inductive coupling.

© 2008 The Japan Institute of Electronics Packaging. Reprinted, with permission, from [Reference Miura and Kuroda49]

A test chip from 2008 (top-right of Figure 1.38 and [Reference Miura, Kohama, Sugimori, Ishikuro, Sakurai and Kuroda41]) confirmed the scalability of communication distance of inductive coupling. Figure 1.44 compares the performance of the test chip with an alternate capacitive coupling interface from 2007. The same data rate of 11 Gb/s at comparable BER was realized using a smaller area for five times the communication distance. Furthermore, communication distance could be extended from 15 to 45 µm with only a 23% drop in data rate to 8.5 Gb/s at the same BER.

Figure 1.44 Performance comparison between inductive and capacitive coupling.

© 2008 The Japan Institute of Electronics Packaging. Reprinted, with permission, from [Reference Miura and Kuroda49]

1.3.4.6 Wireless <3D Integration

While 2.5D integration using TSVs as introduced in Section 1.3.4.3 offers a lower-cost alternative to TSV-based 3D integration, the introduction of TSVs and a silicon interposer, albeit fabricated in a more mature process, still represents a significant cost adder. Furthermore, the integrated package contains three levels of bumps and solder balls – microbumps between chips and interposer, C4 or flip-chip bumps between interposer and package substrate, and solder balls connecting package substrate to the PCB (Figure 1.45a). As a result, thermomechanical stress can occur in three physical interfaces, degrading reliability of the integrated part. The problem is exacerbated by the increasing silicon interposer size to accommodate larger processor chips and/or more integrated chips placed side by side. For instance, the CoWoS-2 integration technology from TSMC supports a large interposer of 1,200 mm² in size. To alleviate the cost and reliability problems of conventional 2.5D integration, inductive coupling (wireless, n_st ≥ 2) has been explored for enhancing <3D integration. In all three solutions of TCI <3D integration in Figure 1.45, both TSVs and microbumps are eliminated. Furthermore, in TCI 2.5D integration, the large silicon interposer in conventional 2.5D integration is replaced by a small piece of silicon interposer between each pair of adjacent chips. Together they add up to attractive cost saving and higher reliability to enhance <3D integration solutions. These solutions will be further discussed in Section 2.3.

Figure 1.45 TCI <3D integration solutions.

1.4.2.1 Motivation for a Near-Field IC Interface

ThruChip Interface (TCI) is a near-field IC interconnect technology that has been developed to address two major challenges facing the IC industry. The first challenge is the slowing of Moore’s law, which calls for innovative More than Moore solutions for 3D IC integration as discussed in Section 1.3. Using inductive coupling, TCI offers a better n_st ≥ 2 IC integration solution than TSV, enabling integration of more than two chips at lower cost while delivering high data rate at low power.

The second challenge addressed by TCI is the performance gap between chip core (computational performance) and I/O (interface communication bandwidth). Enabled by Moore’s law, performance of digital circuits in the chip core has been increasing by about 71% every year. This is the result of an annual increase in transistor speed of about 15% coupled with annual increase in chip core functional density of about 49% (1.15 * 1.49 = 1.71). Based on Rent’s rule, to take full advantage of this increased computational performance, the I/O bandwidth should increase at an annual rate of 46% (1.71^0.7 = 1.46). In reality, however, process scaling only drives an annual I/O bandwidth increase of 28%. While flip-chip packaging is commonplace for high-performance processors today, for many years wirebond was the dominant packaging technology. Since wirebond packaging uses peripheral pads for I/O interconnection, chip I/O functional density improves only linearly with process scaling, by about 11% annually. Together with the annual increase of 15% in transistor speed, total I/O bandwidth improvement from scaling has been around 28% (1.15 * 1.11 = 1.28). To make up for the deficit, circuit innovations have been employed to boost the data rate to sustain a total annual bandwidth increase of about 46% (Figure 1.48).

Figure 1.48 Disparity in performance scaling: chip vs. I/O.

Unfortunately, continuous increase in data rate is not sustainable, because of the high circuit power and off-chip interconnect signal integrity problems that result. For instance, to enable high data rate, a high-speed clock must be distributed across the chip, which requires insertion of buffers to compensate for loss, significantly increasing power consumption of the clock tree. In some cases, I/O power has risen to be more than 30% of total chip power. Therefore, in order to deliver increasing I/O bandwidth without breaking the power budget, instead of disproportionally boosting data rate, a better approach is to increase the number of parallel interconnections. The first step is to shift from using a peripheral to an area array of I/O connection terminals. This has resulted in the wide adoption of flip-chip packaging for high-performance IC. Nevertheless, since the flip-chip bumping process has not been scaling as fast as the IC fabrication process, flip-chip bump pitch and hence I/O interconnection density scaling has not been keeping pace with IC performance increase in terms of process node scaling, as shown in Figure 1.49, based on the industry roadmap published in 2015 [52]. Consequently, an alternate area array interconnect technology that follows Moore’s law scaling is desired.

Figure 1.49 Scaling comparison: flip-chip bump pitch vs. process.

The Wide I/O Mobile DRAM solution introduced in Section 1.3.4.2 was a solution that used TSV to create a large number of parallel interconnections to deliver high I/O bandwidth. But as previously noted, TSV carries a significant cost premium both because of the added processing cost and the area overhead resulting from its large keep-out zone. For a memory chip, the added manufacturing cost of TSV can amount to 10% of the total cost. Furthermore, thermomechanical stresses can lead to loss in reliability. The problem is magnified by the tens of thousands of TSVs and microbumps utilized by each chip. Therefore, a lower fabrication cost, lower area overhead, and higher reliability solution is warranted.

1.4.2.2 Characteristics and Merits of TCI

TCI is an inductive near-field coupling, wireless interconnect technology offering an alternate solution to TSV for 3D IC integration and for delivering high interface bandwidth at low power. Figure 1.50 depicts the basic structure of TCI. Specifically, it consists of a pair of coupled coils that communicate by varying the magnetic field linked between them (Figure 1.50a). Each coil is implemented as a multiturn loop (n = number of turns) across multiple interconnect layers (m = number of layers) as part of the BEOL IC fabrication process (Figure 1.50b). The basic transceiver consists of simple digital CMOS circuits – the transmitter is an H-bridge circuit that switches current in the transmitter coil at the transition of Txdata, while the receiver is a sense-amplifier flip-flop that detects the resultant small voltage magnetically induced in the receiver coil to create Rxdata (Figure 1.50c). With proper mitigation measures, electromagnetic interference (EMI) from the coils can be made negligible, allowing transmitter and receiver circuits to be placed directly underneath the coils with no keep-out zone to form a compact I/O design (Figure 1.50d). In fact, test chip results have shown that TCI coils can be placed directly on top of active circuits and memory cells, including SRAM, NAND, and DRAM, with no appreciable degradation.

Figure 1.50 Basic structure of TCI.

(c) and (d) © 2017 IEEE. Reprinted, with permission, from [Reference Kuroda51]

Table 1.6 enumerates the general merits of TCI given its characteristics, and the value delivered to 3D IC integration and to a low-power, high-bandwidth chip interface respectively. Meanwhile, Table 1.7 highlights how TCI compares favorably against TSV. In contrast to TSV, which requires mechanical processing, TCI is an electrical and digital solution fabricated as part of the standard wafer process. As a result, TCI incurs much lower manufacturing cost. Because OSAT is not involved in implementing the interconnection, TCI can utilize the existing manufacturing ecosystem. Furthermore, unlike TSV, TCI can be placed directly over circuits, resulting in minimal area overhead. Additionally, being a contactless interconnection, TCI eliminates the need for ESD protection circuits, resulting in much smaller parasitic capacitance and hence significantly lower power and higher speed.

Table 1.7. Comparison of TCI and TSV.

	TSV	TCI
Connection mechanism	Mechanical	Electrical
Fabrication process	Additional steps required	Standard CMOS
Dimensional scaling	Difficult	Easy
Yield	Low, difficult to improve	High ($\approx$100%)
Ecosystem	New model required	Conventional
Cost adder	>40%	A few %
Placement	Dedicated area with keep-out	Flexible
Bandwidth	<512 Gb/s	>512 Gb/s
ESD protection	Required	Not required
Power consumption	High	Low

Source: © 2017, IEEE. Reprinted, with permission, from [Reference Kuroda51].

In summary, TCI is a low-cost, low-power, high-bandwidth technology with high interconnection density and reliability, which enables flexible and high-level integration of ICs in small form factor. Furthermore, its PPA will continue to improve as process scales under Moore’s law, enabling it to advance together with IC performance.

The table in Figure 1.51 from [Reference Ishikuro and Kuroda50] illustrates how TCI performance scales with process. Under this scaling scenario, coupling coefficient and crosstalk and hence signal-to-noise ratio will remain unchanged, while both aggregated data rate/area and energy/bit will improve drastically in a cubic fashion. This represents an optimistic scenario – in reality, supply voltage and chip thickness may not scale as fast as transistor size. Nevertheless, it illustrates how TCI performance will benefit from scaling in transistor size, power supply voltage, and chip thickness simultaneously. Hence, there is plenty of headroom for its performance to improve as process scaling continues.

Figure 1.51 TCI performance scaling scenario.

© 2010 IEEE. Reprinted, with permission, from [Reference Ishikuro and Kuroda50]

The potential of TCI has been demonstrated in multiple test chips. In 2010, a data rate of 30 Gb/s/channel and 2.2 Tb/s/mm² was reported in [Reference Take, Miura and Kuroda53], an energy efficiency of 0.01 pJ/b in [Reference Miura, Shidei, Yuxiang, Kawai, Takatsu, Kiyota, Asano and Kuroda54], and successful random memory access to a stack of 128 NAND flash chips in [Reference Saito, Miura and Kuroda55].

1.4.2.3 Application of TCI

Given the myriad of benefits delivered by TCI, it is expected to offer improvement to a large variety of applications. Figure 1.52 illustrates some of these applications.

Figure 1.52 Example TCI applications.

© 2010 IEEE. Reprinted, with permission, from [Reference Ishikuro and Kuroda50]

For instance, a conventional SSD with a stack of eight wirebonded NAND flash memory chips can be replaced with a stack of 64 TCI-equipped chips. Even with eight times the capacity, the TCI-enabled SSD would use fewer packages (9→1) and bond wires (1500→200), hence be lower cost with lower assembly complexity in a smaller form factor, at almost half the power (Figure 1.53). Additional details are provided in Section 2.7.

Figure 1.53 High-capacity SSD enabled with TCI.

© 2010 IEEE. Reprinted, with permission, from [Reference Saito, Sugimori, Kohama, Yoshida, Miura, Ishikuro, Sakurai and Kuroda56]

On the other hand, using TCI, a processor can be directly connected to a stack of SRAM chips fabricated in a different process optimized for SRAM and supplied with a different voltage (Figure 1.54, [Reference Niitsu, Shimazaki, Sugimori, Kohama, Kasuga, Nonomura, Saen, Komatsu, Osada, Irie, Hattori, Hasegawa and Kuroda57–Reference Osada, Saen, Okuma, Niitsu, Shimazaki, Sugimori, Kohama, Kasuga, Nonomura, Irie, Hattori, Hasegawa and Kuroda58]). This would offer an alternate memory solution to DRAM with better energy efficiency and bandwidth per unit area. Additional details are provided in Sections 2.3.1 and 4.1.

Figure 1.54 Processor and SRAM stack integrated with TCI.

(a) © 2009 IEEE. Reprinted, with permission, from [Reference Niitsu, Shimazaki, Sugimori, Kohama, Kasuga, Nonomura, Saen, Komatsu, Osada, Irie, Hattori, Hasegawa and Kuroda57]; (b) Copyright 2009 The Japan Society of Applied Physics [Reference Osada, Saen, Okuma, Niitsu, Shimazaki, Sugimori, Kohama, Kasuga, Nonomura, Irie, Hattori, Hasegawa and Kuroda58]

1.4.3.1 Motivation for a Near-Field Coupled Module Connector

TCI interconnect technology offers a versatile low-power, high-performance solution for connecting multiple IC chips directly together. However, it is not always possible to integrate all the IC chips that need to communicate with each other into a single package. For instance, to build a large-scale computer system such as a supercomputer, it is necessary to modularize smaller building blocks such as a graphic or memory card. This is done for multiple reasons, including cost, design simplicity, ease of customization, serviceability (ease of replacing defective parts), and scalability. As a result, while it is best to have minimal communication distance to suppress signal integrity problems and interface power, it is also necessary to develop interface technology that supports long communication distance, traversing multiple printed circuit boards and connectors.

Interface technology that supports long communication distance must address similar challenges of delivering high bandwidth at low power as is described in Section 1.4.1. As an illustration, the communication data rate between the application processor and display in a smartphone continues to climb exponentially as new display format emerges (Figure 1.55, [Reference Kosuge59]). Full HD format, which has enjoyed widespread adoption starting around 2016, requires a date rate of 3 Gb/s. To support the next upgrade in resolution to 4K/8K, the maximum data rate will need to increase to 50 Gb/s. Even higher data rates will be necessary to support richer color and higher refresh rate. With these trends as the backdrop, the MIPI Alliance responsible for setting standards for mobile applications has created its high-performance interface physical layer M-PHY specification to support 10 Gb/s-class internal data communication.

Figure 1.55 Data rate as a function of display format.

© 2016 Atsutake Kosuge [Reference Kosuge59]

Meanwhile, the widely adopted DDR external memory interface, USB and PCIe peripheral interfaces, automotive LAN interface, as well as satellite processor-memory interfaces are all experiencing similar increases in data rate (Figure 1.56, [Reference Kosuge59]).

Figure 1.56 Data rate trends of widely adopted interfaces.

© 2016 Atsutake Kosuge [Reference Kosuge59]

With the exception of automotive LAN interface, all interfaces have a data rate exceeding 1 Gbps/lane. Given that communication distance in these interfaces is longer than a centimeter, at such high data rates, signal transmission is subject to transmission line effects. (Remember that a PCB interconnect only needs to be longer than 1.67 mm to appear as a transmission line to a 1 Gbps signal.) As a result, signal transmission is subject to reflection and hence distortion at any discontinuity in characteristic impedance Z₀ along the interface (Section 1.2.3).

Figure 1.57 depicts a typical interconnect structure for some of these interfaces constructed with modules. To minimize signal distortion, the signal must see Z₀ close to being constant as it traverses this interconnect structure. For practical reasons, the default Z₀ for most applications is 50 Ω. Therefore, the target Z₀ for module PCB1, connector1, main PCB, connector2, and module PCB2 should all be 50 Ω. As data rate goes up such that smaller and smaller interconnect features begin to exhibit transmission line effects, designing for constant Z₀ becomes increasingly challenging. Z_0, which governs how an electromagnetic signal propagates, is determined by the electric and magnetic field patterns around the transmission line. It is therefore highly dependent on any large metallic component of the interconnect structure. Conversely, it is easier to control Z₀ of an interconnect when there is a large inherent metallic component. As a result, it is easier to control Z₀ of a PCB interconnect than a connector since the former generally contains large voltage and ground planes running parallel to signal paths while the latter does not (Figures 1.57 and 1.58). Figure 1.59 shows the simulated signal degradation due to an interconnect consisting of a backplane connector plus a 5 cm PCB trace. The significant degradation due to the connector is evident in both the frequency and time domain.

Figure 1.57 A typical interconnect structure in a modular system.

© 2016 Atsutake Kosuge [Reference Kosuge59]

Figure 1.58 Internal structure of a backplane connector.

© 2016 Atsutake Kosuge [Reference Kosuge59]

Figure 1.59 Simulated signal degradation of a backplane interconnect.

© 2016 Atsutake Kosuge [Reference Kosuge59]

To compensate for the severe degradation due to transmission line effects, complicated equalization circuits are commonplace in the implementation of high-speed interfaces. Common equalization circuit solutions include TX (transmitter) deemphasis to boost high-frequency components while attenuating low-frequency components of the transmitted signal (Figure 1.60a, [Reference Meghelli, Rylov, Bulzacchelli, Rhee, Rylyakov, Ainspan, Parker, Beakes, Chung, Beukema, Pepeljugoski, Shan, Kwark, Gowda and Friedman60]), continuous time linear equalizer (CTLE) to boost high-frequency components of the received signal (Figure 1.60b, [Reference Shekhar, Jaussi, O’Mahony, Mansuri and Casper61]), and decision feedback equalizer (DFE), which determines how to compensate each received bit based on the preceding bit pattern (Figure 1.60c, [Reference Musah, Jaussi, Balamurugan, Hyvonen, Hsueh, Keskin, Shekhar, Kennedy, Sen, Inti, Mansuri, Leddige, Horine, Roberts, Mooney and Casper62]). As the name implies, equalization circuits serve to equalize the transmission gain of an interconnect across different frequencies. For proper data transmission, such circuits are necessary to compensate for the wild variation in gain over frequency, as shown in Figure 1.59a. While CTLE is relatively simple, TX deemphasis and DFE circuits grow in complexity as the interconnect complexity increases. Equalization circuits can therefore consume a lot of both power and chip area, significantly increasing interface power and area overhead.

Figure 1.60 Common equalization circuit solutions.

© 2016 Atsutake Kosuge [Reference Kosuge59]

Another transmission line effect degrading signal integrity is crosstalk. In addition to controlling characteristic impedance, large voltage and ground planes also serve to suppress crosstalk since they limit the spreading of electric and magnetic fields from one transmission line to another. Conversely, the lack of such planes in a connector contributes to not only poorly controlled characteristic impedance, but also significant crosstalk. As a result, from an electrical signal integrity standpoint, a connector is generally the weakest link in an interconnect structure for a high-speed interface.

From a mechanical standpoint too, the connector has weaknesses in terms of environmental robustness given that a connection is made through physical contact. This can be problematic when the connector must operate under harsh environmental conditions, such as when it is used in consumer applications and subject to user mishandling, or in an automotive and subject to heat and vibration as well as high density of contaminants, or in a satellite and subject to stressful conditions during launch and a harsh environment in space. In particular, to allow for physical contact to make a connection, connector pins must be exposed and hence subject to deterioration due to environmental conditions. Furthermore, strong vibration can weaken the connection, especially when it is solderless. On the other hand, water can create a short, while contaminants can create a short or increase contact resistance. Additionally, for applications where the connector must endure multiple cycles of mating and disengaging, the physical connection can be weakened through wear and tear.

The ever-shrinking form factor demanded by applications such as mobile and IoT poses additional challenges to the conventional connector. Smaller physical dimensions further degrade the environmental robustness of the connector. Smaller pins and pin pitch are more susceptible to the effects of contaminants and shorting, and wear and tear. Furthermore, smaller pins result in a smaller contact force making it easier to break a connection through vibration. On the other hand, since connector manufacturing involves mechanical processing, it is difficult to scale down its dimensions, making it challenging to support not only a shrinking form factor but also increasing interconnection density.

As a result, an alternate connector technology is necessary to enable better characteristic impedance and crosstalk control for high-speed interfaces, better robustness for operating under harsh environment, and better scaling to support increasing pin count in shrinking form factor.

While TCI can address a lot of these challenges, it suffers from two limitations when applied to a connector. First, since the coil in the coupler is inductive, its impedance varies with frequency. As a result, when it is used to connect two transmission lines, it creates a discontinuity in the characteristic impedance of the interconnect. This is demonstrated by the simulated received signal through a TCI connector attached to a 5 cm, 50 Ω transmission line in Figure 1.61. The impedance discontinuity results in large ripples in the frequency domain gain, and closes the data eye in time domain. Second, the coil inductance together with its parasitic capacitance create a resonance circuit. Since coil size varies linearly with communication distance, the large communication distance required in connector applications means that the coil size must grow, simultaneously increasing its inductance and capacitance, resulting in a lower resonant frequency. Consequently, a TCI connector has a limited bandwidth.

Figure 1.61 Simulated received signal through a TCI connector and transmission line.

© 2016 IEEE. Reprinted, with permission, from [Reference Kosuge, Kadomoto and Kuroda63]

1.4.3.2 Characteristics and Merits of TLC Technology

TLC is an electromagnetic near-field coupling, wireless interconnect technology developed to address the challenges faced by conventional connectors enumerated in the previous section. Figure 1.62a depicts the basic structure of TLC, which consists of two pairs of differential transmission lines aligned face to face with each other and can be implemented in a PCB manufacturing process. Each pair is designed to have well-controlled characteristic impedance and minimal crosstalk by virtue of a proximal ground plane (Figure 1.62b). This is evident from the simulated transmission gain in the frequency domain of an example TLC connector in Figure 1.63, which exhibits relative flatness over a wide frequency range. Note that since TLC is a wireless technology, there is no DC gain and hence the curve falls off at low frequency.

Figure 1.62 Basic structure of TLC.

(a) and (b) © 2016 Atsutake Kosuge [Reference Kosuge59]; (c) © 2015 IEEE. Reprinted, with permission, from [Reference Kosuge, Hashiba, Kawajiri, Hasegawa, Shidei, Ishikuro, Kuroda and Takeuchi64]

Figure 1.63 Transmission gain of an example TLC connector.

© 2015 IEEE. Reprinted, with permission, from [Reference Kosuge, Ishizuka, Taguchi, Ishikuro and Kuroda65]

Figure 1.62c shows the basic structure of the TLC transceiver. It consists of a simple 50 Ω terminated current mode logic driver and a hysteresis comparator in the receiver. In contrast to conventional connectors, the well-controlled characteristic impedance of a TLC connector significantly reduces the need for complex equalization circuits.

Table 1.8 enumerates the general merits of TLC given its characteristics and how they address the challenges of implementing a high-speed interface that includes connectors. It lists the characteristics that strengthen the environmental robustness of the connector. Furthermore, it explains how it enables a low-power and high-bandwidth interface at a lower cost than conventional mechanical connectors. While the PCB manufacturing process does not scale as fast as the IC fabrication process, it enjoys better scaling than the mechanical processes used to manufacture conventional connectors. As a result, there is room for scaling the TLC connector form factor. Besides, using digital CMOS circuits for its transceiver allows its PPA to improve as IC process scales. Finally, not requiring level shifters can be a real benefit when more and more heterogeneous subsystems are connected together as the semiconductor continues to proliferate, especially in IoT and automotive applications.

1.4.3.3 Application of TLC

Given the myriad of benefits delivered by TLC, it is expected to offer improvement to a large variety of applications. Figure 1.64 from [Reference Kuroda51] illustrates some of these applications, which range from consumer applications, including memory cards, displays, smartphones, and PC memory DIMM modules, to automotive and space applications.

Figure 1.64 Example TLC applications.

© 2017 IEEE. Reprinted, with permission, from [Reference Kuroda51]

For instance, TLC can enable a low-cost, low-power, high-bandwidth solution to build a modular smartphone with various heterogeneous subsystems, with low profile and small footprint (Figure 1.65, [Reference Kosuge, Ishizuka, Kadomoto and Kuroda68]), while offering headroom for future PPA improvement. Further discussion of TLC application in smartphones is provided in Section 3.3.

Figure 1.65 A modular smartphone design.

© 2015 IEEE. Reprinted, with permission, from [Reference Kosuge, Ishizuka, Kadomoto and Kuroda68]