Book contents
- Frontmatter
- Contents
- Preface
- Introduction
- Acknowledgments
- Contributors
- Acronyms and Abbreviations
- Boolean Models and Methods in Mathematics, Computer Science, and Engineering
- Part I Algebraic Structures
- Part II Logic
- Part III Learning Theory and Cryptography
- Part IV Graph Representations and Efficient Computation Models
- Part IV Applications in Engineering
- 15 Hardware Equivalence and Property Verification
- 16 Synthesis of Multilevel Boolean Networks
16 - Synthesis of Multilevel Boolean Networks
from Part IV - Applications in Engineering
Published online by Cambridge University Press: 05 June 2013
- Frontmatter
- Contents
- Preface
- Introduction
- Acknowledgments
- Contributors
- Acronyms and Abbreviations
- Boolean Models and Methods in Mathematics, Computer Science, and Engineering
- Part I Algebraic Structures
- Part II Logic
- Part III Learning Theory and Cryptography
- Part IV Graph Representations and Efficient Computation Models
- Part IV Applications in Engineering
- 15 Hardware Equivalence and Property Verification
- 16 Synthesis of Multilevel Boolean Networks
Summary
Boolean Networks
Introduction
Two-level logic minimization has been a success story both in terms of theoretical understanding (see, e.g., [15]) and availability of practical tools (such as espresso) [2, 14, 31, 38]. However, two-level logic is not suitable to implement large Boolean functions, whereas multilevel implementations allow a better tradeoff between area and delay. Multilevel logic synthesis has the objective to explore multilevel implementations guided by some function of the following metrics:
(i) The area occupied by the logic gates and interconnect (e.g., approximated by literals, which correspond to transistors in technology-independent optimization);
(ii) The delay of the longest path through the logic;
(iii) The testability of the circuit, measured in terms of the percentage of faults covered by a specified set of test vectors, for an appropriate fault model (e.g., single stuck faults, multiple stuck faults);
(iv) The power consumed by the logic gates and wires.
Often good implementations must satisfy simultaneously upper or lower constraints placed on these parameters and look for good compromises among the cost functions.
It is common to classify optimization as technology-independent versus technology-dependent, where the former represents a circuit by a network of abstract nodes, whereas the latter represents a circuit by a network of the actual gates available in a given library or programmable architecture. A common paradigm is to first try technology-independent optimization and then map the optimized circuit into the final library (technology mapping).
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- Publisher: Cambridge University PressPrint publication year: 2010
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