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6 - PIPELINED PROCESSORS

Published online by Cambridge University Press:  05 June 2012

Harvey G. Cragon
Affiliation:
University of Texas, Austin
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Summary

INTRODUCTION

Chapter 5 described the design of serial execution model processors that have either hardwired or microprogrammed control. In this chapter, the techniques used in pipelining are described. Pipelining, sometimes called assembly line processing, has its roots in manufacturing technology. Auto pioneer Henry Ford is generally credited with developing the assembly line for constructing the Model T automobile. There is an unverified story that Ford visited a packing plant in Chicago and saw the disassembly of beef cattle. He is said to have observed that if one can take something apart on a disassembly line then one can do the reverse. Thus the germ of an idea was planted.

A pipelined processor has functional units for each function performed in the interpretation of an instruction. In some cases, the functional units perform more than one operation. Instructions flow into the pipeline and results flow out. The transit time (latency) through the pipeline may be long, but in most cases it is the rate of flow through the pipeline that is important. This is also true of the pipeline that brings water into your home. You don't care how many miles or days it took the water to get to you from the lake; you are only concerned that the flow rate is sufficient.

Base Pipelined Processor

As discussed in Chapter 5 and shown in Figure 5.4, the steps required for interpreting an instruction of the load/store ISA are as follows:

  1. Fetch instruction.

  2. Decode instruction.

  3. Read registers.

  4. Execute.

  5. Compute effective addresses for data and branch target.

  6. Read or write memory.

  7. Write to register.

  8. Test for a branch.

  9. Increment program counter.

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Chapter
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Publisher: Cambridge University Press
Print publication year: 2000

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  • PIPELINED PROCESSORS
  • Harvey G. Cragon, University of Texas, Austin
  • Book: Computer Architecture and Implementation
  • Online publication: 05 June 2012
  • Chapter DOI: https://doi.org/10.1017/CBO9781139164412.007
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  • PIPELINED PROCESSORS
  • Harvey G. Cragon, University of Texas, Austin
  • Book: Computer Architecture and Implementation
  • Online publication: 05 June 2012
  • Chapter DOI: https://doi.org/10.1017/CBO9781139164412.007
Available formats
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To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Google Drive.

  • PIPELINED PROCESSORS
  • Harvey G. Cragon, University of Texas, Austin
  • Book: Computer Architecture and Implementation
  • Online publication: 05 June 2012
  • Chapter DOI: https://doi.org/10.1017/CBO9781139164412.007
Available formats
×