8 - Frequency division
Published online by Cambridge University Press: 09 August 2009
Summary
Introduction
PLLs designed for frequency synthesis employ a variable-frequency divider, which provides programmability and enables the use of reference crystal oscillators. The two main issues related to the design of the frequency divider are the high input frequency and the programmability of the division factor. As will be made clearer in this chapter, wide variations of the division factor and high input frequency are opposing requests. To some extent, higher operation frequency can be traded against power consumption. However, as we will show, smart architectural choices can allow for much higher frequency of operation with the same power consumption and technology process. The input sensitivity that is the minimum required amplitude of the input signal is also of great concern in high-speed dividers.
Digital dividers are based on either flip-flops or latches, using either static or dynamic logics. Analogue implementations of divide-by-two circuits relying on injection locking or parametric amplification also exist. Depending on their implementation, dividers have different noise generation mechanisms. However, a lower phase noise generally demands higher power consumption.
This chapter discusses typical techniques for realizing programmable dividers, with particular emphasis on such topologies as allow for maximum speed in a given semiconductor process. The circuit implementations of the building blocks will be reviewed. Finally, methods for predicting the noise of digital frequency dividers will be examined.
Digital frequency dividers
Digital frequency dividers by M are modulo-M counters.
Information
- Type
- Chapter
- Information
- Integrated Frequency Synthesizers for Wireless Systems , pp. 182 - 210Publisher: Cambridge University PressPrint publication year: 2007
References
, A study of locking phenomena in oscillators, P. IEEE, 61, Oct. 1973, 1380–5.CrossRefGoogle Scholar
and , CMOS high-speed dual-modulus frequency divider for RF frequency synthesis, IEEE J. Solid-St. Circ., 30, Feb. 1995, 93–100.CrossRefGoogle Scholar
and , A stabilization technique for phase-locked frequency synthesizers, IEEE J. Solid-St. Circ., 38, Jun. 2003, 888–94.Google Scholar
et al., A high-speed multimodulus HBT prescaler for frequency synthesizer applications, IEEE J. Solid-St. Circ., 26, Oct. 1991, 1362–7.CrossRefGoogle Scholar
, High-speed architecture for a programmable frequency divider and a dual-modulus prescaler, IEEE J. Solid-St. Circ., 31, May 1996, 744–8.CrossRefGoogle Scholar
, , et al., A family of low-power truly modular programmable dividers in standard 0.35-µm CMOS technology, IEEE J. Solid-St. Circ., 35, Jul. 2000, 1039–45.CrossRefGoogle Scholar
and , A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-µm CMOS, IEEE J. Solid-St. Circ., 31, Jul. 1996, 890–7.CrossRefGoogle Scholar
and , A 5.3-GHz programmable divider for HiPerLAN in 0.25-µm CMOS, IEEE J. Solid-St. Circ., 35, Jul. 2000, 1019–24.CrossRefGoogle Scholar
M. H. Perrot, Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizer, Ph. D. thesis, Massachusetts Institute of Technology, Cambridge, MA, 1997.
, and , A 1.5 GHz, sub-2 mW CMOS dual modulus prescaler, in Proc. IEEE Custom Integrated Circuits Conf., San Diego, CA, 1999, 613–16.Google Scholar
, , and , A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier, IEEE J. Solid-St. Circ., 38, Jun. 2003, 866–74.Google Scholar
and , A 1-V 5.2-GHz CMOS synthesizer for WLAN applications, IEEE J. Solid-St. Circ., 39, Nov. 2004, 1873–82.CrossRefGoogle Scholar
et al., A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11 a/b/g wireless LAN, IEEE J. Solid-St. Circ., 39, Dec. 2004, 2239–49.CrossRefGoogle Scholar
, and , A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2) latch and its application in a dual-modulus prescaler, IEEE J. Solid-St. Circ., 34, Oct. 1999, 1400–4.Google Scholar
and , High-speed CMOS circuit technique, IEEE J. Solid-St. Circ., 24, Feb. 1989, 62–70.CrossRefGoogle Scholar
and , Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks, IEEE J. Solid-St. Circ., 31, Mar. 1996, 456–65.CrossRefGoogle Scholar
B. De Muer and M. Steyaert, A single ended 1.5 GHz 8/9 dual modulus prescaler in 0.7-µm CMOS technology with low phase noise and high input sensitivity, in Proc. 1998 Eur. Solid-State Circuits Conf., 1998, 256–9.
and , A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC), IEEE J. Solid-St. Circ., 34, Jan. 1999, 97–102.CrossRefGoogle Scholar
, FET scaling in domino CMOS gates, IEEE J. Solid-St. Circ., 20, Oct. 1985, 1067–71.CrossRefGoogle Scholar
, Modeling phase noise in frequency dividers, IEEE T. Ultrason. Ferr., 37, Jul. 1990, 307–15.CrossRefGoogle Scholar
, Jitter and phase noise in frequency dividers, IEEE T. Instrum. Meas., 50, Oct. 2001, 1241–3.CrossRefGoogle Scholar
, , , and , Phase noise in digital frequency dividers, IEEE J. Solid-St. Circ., 39, May 2004, 775–84.CrossRefGoogle Scholar
and , A new low-noise 100-MHz balanced relaxation oscillator, IEEE J. Solid-St. Circ., 25, Jun. 1990, 692–8.CrossRefGoogle Scholar
and , Characterization of frequency stability in precision frequency sources, P. IEEE, 79, Jun. 1991, 952–60.CrossRefGoogle Scholar
Accessibility standard: Unknown
Accessibility compliance for the PDF of this book is currently unknown
and may be updated in the future.