In Chapter 4, we discussed techniques for obtaining minimal two-level AND–OR or OR–AND realizations. In the present chapter we generalize the discussion to the synthesis of multi-level realizations, i.e., those that contain more than two levels of logic gates. Such realizations are important since they often require less area and delay compared to the corresponding two-level realizations and hence are more practical. However, unlike two-level realizations, it is difficult to obtain provably optimal multi-level realizations because of the much larger design space available for exploration. Thus, the goal of multilevel logic synthesis is to obtain the best possible realization that targets some design objective such as area reduction while meeting some design constraint such as circuit delay.

There are two phases in multi-level logic synthesis; these are the technology-independent and technology-dependent phases. In the technology-independent phase, the circuit is improved for the targeted design criterion, using the laws of Boolean algebra. In the technology-dependent phase, the resultant circuit is mapped to a library of gates available for the given semiconductor technology. We shall discuss the techniques involved in both phases.

Technology-independent synthesis

Technology-independent multi-level logic synthesis is carried out with the help of various logic transformations that preserve the input–output behavior of the circuit. The most important transformations are factoring, decomposition, extraction, substitution, and elimination. We discuss these transformations next.