Predicting the future is the realm of prophets and gamblers. Generally speaking, engineers belong to neither of these groups. However, it is evident that the trend in high-performance transistors is towards smaller and smaller devices, so we might reasonably expect this to continue into the near future. This miniaturizing trend has led, in the early part of the 21st century, to much talk about nanoelectronics. In my opinion, nanoelectronics does not mean, contrary to popular belief, merely the scaling down of transistors to devices with feature sizes of the order of tens of nanometres. If it did, then present-day devices, such as InGaP/GaAs HBTs with basewidths of around 30 nm, Si MOSFETs with channel lengths of ≈40 nm, and InAlAs/InP HJFETs with channel thicknesses of a few nanometres, would already qualify as nanotransistors.

What nanoelectronics implies, to me at least, is the fabrication of transistors from the ‘bottom up’, rather than from the ‘top down’. The latter process is the one that applies to all the HBTs, MOSFETs, and HJFETs discussed in earlier chapters: it involves the making of something small from something large using photolithographic masking techniques. Contrarily, a true nanotransistor is built-up from something even smaller, such as a molecule or a nanoparticle. This opens up opportunities for new methods of self-assembly (perhaps using biological recognition), and for new 3-D circuitry (perhaps using a molecular backbone), that cannot be matched using conventional processing techniques.