Introduction

Tangram is a VLSI-programming language based on CSP, and has much in common with the programming language OCCAM [INM89] (see Section 2.7 for some of the differences). The main construct of Tangram is the command. Commands are either primitive commands, such as a?x and x := x + 1, or composite commands, such as R; S and R ∥ S, where R and S are commands themselves.

Execution of a command may result in a number of communications with the environment through external ports. Another form of interaction with the environment is the reading from and writing into external variables. A Tangram program is a command without external variables, prefixed by an explicit definition of its external ports.

Not all compositions of commands are valid in Tangram. For instance, in a sequential composition the two constituent commands must agree on the input/output direction of their common ports. Also, two commands composed in parallel may not write concurrently into a common variable. Similarly, concurrent reading from and writing into a common variable is not allowed. Section 6.1 defines the syntax of Tangram, including these composition rules. The meaning of each command is described informally.

For a subset of the Tangram commands the handshake-process denotations are given in Section 6.3. This subset is referred to as Core Tangram.

Tangram

The main syntactic constructs of Tangram are program, command, guarded-command set, and expression. With each construct we associate a so-called alphabet structure: a set of typed ports and variables.

Introduction

Handshake circuits are proposed as an intermediary between communicating processes (Tangram programs) and VLSI circuits. Chapter 7 describes the translation of Tangram programs into handshake circuits. This chapter is concerned with the realization of handshake circuits as efficient and testable VLSI circuits. First we observe that the fine-grained parallelism available in VLSI circuits matches the fine-grained concurrency in handshake circuits nicely. The mapping of handshake circuits to VLSI circuits can therefore be relatively direct.

A rather naive mapping is suggested by the following correspondence:

1. a channel corresponds to a set of wires, one per symbol;

2. an event with name a corresponds to a voltage transition along wire a;

3. each handshake component corresponds to a VLSI circuit that satisfies the specification at the transition level.

There is no doubt that the above mapping can result in functional circuits. In general, however, the resulting circuits will be prohibitive in size, poor in performance, probably hard to initialize, and impractical to test for fabrication faults. Concerns for circuit size, performance, initialization and testability are therefore recurring themes in this chapter.

A full treatment of all relevant VLSI-realization issues is beyond the scope of this monograph. Issues that directly relate to (properties of) handshake circuits have been selected for a relatively precise treatment; other topics are sketched more briefly. This chapter discusses:

• peephole optimization: the replacement of subcircuits by cheaper ones;

• relaxation of the receptiveness requirement of handshake processes;

• […]

Introduction

So far the quiescent trace set of a handshake process was specified in one of the following forms: by enumeration, by a predicate, by a state graph, or by parallel composition of other handshake processes.

For many handshake processes none of the above forms may be convenient. An example of such a process is the process that first behaves like P and then, “after successful termination of P”, behaves like Q. Of course, such sequential composition of the handshake processes P and Q requires a notion of successful termination of a process. A sequential handshake process is a handshake process in which that notion is incorporated.

The aim of this chapter is to develop a model for sequential handshake processes and a calculus for these processes. An important application of this calculus is the description of the handshake components required for the compilation of Tangram. Another application is the semantics of Tangram itself.

Sequential handshake processes

A sequential handshake process is a handshake process, some of whose traces are designated as terminal traces, i.e. traces that lead to successful termination. In a sequential composition these terminal traces can be prefixed to traces of the subsequent sequential handshake process.

Let T denote the set of quiescent traces and let U denote the set of terminal traces of sequential handshake process P. Sets T and U must satisfy a number of conditions, which are introduced informally.

Introduction

The topic of this chapter is the translation of Tangram programs into handshake circuits. Let T be a Tangram program. In Chapter 6 we have defined the meaning of T as the handshake process H-T. The translation to handshake circuits is presented as a mathematical function C, from the set of Tangram programs to the set of handshake circuits. Thus, C-T is a handshake circuit, and handshake process ∥.C.T is the behavior of that circuit. Function C is designed such that

where .P was defined as #[: P] (see Definition 6.7). That is, the translation preserves all the nondeterminism of the program. From a practical viewpoint it is sufficient to realize

in which the behavior of the handshake circuit is a refinement of the handshake behavior of the Tangram program. It may be expected that this relaxed form results in cheaper handshake circuits. The advantage of defining the most nondeterministic handshake circuit of T is that alternative translation functions that synthesize more deterministic circuits can readily be derived from it. Some of these alternatives will be indicated.

Also, we have chosen to translate a Tangram program into the handshake circuit with the most internal parallelism. In particular, all guards of a guarded command are evaluated in parallel, as are the two subexpressions of a binary operation. In general this leads to the fastest implementation, but not necessarily the most area-efficient one. If the VLSI programmer wishes a more sequential handshake circuit he can specify such at the Tangram level.

Introduction

A handshake is a means of synchronization among communicating mechanisms. In its simplest form it involves two mechanisms connected by a pair of so-called links, one for sending signals and one for receiving signals. The sending of a signal and the reception of a signal are atomic actions, and constitute the possible events by which a mechanisms can interact with its environment.

A signal sent by one mechanism is bound to arrive at the other mechanism, after a finite, non-zero amount of time. Hence, this form of communication is asynchronous; the sending and the arrival of a signal correspond to two distinct events. It is assumed that a link allows at most one signal to be on its way. Consequently, a signal sent must arrive at the other end of the link before the next one can be sent. When the traveling time of a signal along the link is unknown, the only way to know that a signal has arrived at the other side is to be so informed by the other mechanism. The other link in the pair performs the acknowledgement.

Such a causally ordered sequence of events is called a handshake. The two mechanisms involved play different (dual) roles in a handshake. One mechanism has the active role: it starts with the sending of a request and then waits for an acknowledgement. The other mechanism has the passive role: it waits for a request to arrive and responds by acknowledging.

Too often there is thought to be a dichotomy between science and engineering: science as a quest for knowledge and understanding, and engineering as the art of constructing useful objects. This book, based on the author's experience in leading a silicon compilation project at Philips Research, is exceptional in that it very convincingly demonstrates the effectiveness of combining the scientific method with sound engineering practices.

Aimed at bridging the gap between program construction and VLSI design, the research reported in this book extends over an unusually wide spectrum of disciplines, ranging from computer science and electrical engineering to logic and mathematics. In this exciting arena we encounter such topics as the power dissipation of an assignment statement, the mathematical theory of handshake circuits, the correctness proof of a compiler, and the problem of circuit initialization without reset wires, to mention just a few.

Such a multi-faceted study can be successful only if it is able to demonstrate a clear separation of concerns. In this respect, Kees van Berkel does an admirable job: his concept of handshake circuits provides an extremely elegant interface between algorithm design on the one hand and circuit implementations on the other. This separation between ‘what’ and ‘how’, which many researchers and practitioners find difficult to apply, turns out to be amazingly fruitful, as the readers of this book are encouraged to discover for themselves. In my opinion we are, with the publication of this book, witnessing a major step forward in the development of the discipline of VLSI programming.

This book is about the design of digital VLSI circuits. Whereas LSI circuits perform basic functions such as multiplication, control, storage, and digital-to-analog conversion, VLSI circuits contain complex compositions of these basic functions. In many cases all data and signal processing in a professional or consumer system can be integrated on a few square centimeters of silicon. Examples of such “systems on silicon” can be found in:

• Disc (CD) players,

• Disc Interactive (CDI) players,

• Compact Cassette (DCC) players,

• Audio Broadcast (DAB) receivers,

• radios and mobile telephones,

• High-Definition TeleVision (HDTV) sets,

• video recorders,

• processors,

• car-navigation systems,

• processors, and

• test and measurement systems.

These systems generally process analog as well as digital signals, but the digital circuits dominate the surface of an IC. The memory needed for storing intermediate results often covers a significant fraction of the silicon area.

Systems on silicon are tending to become more complex and are tending to increase in number. The increase in complexity follows from advances in VLSI technology, and the rapid growth of the number of transistors integrated on a single IC. The constant reduction of the costs of integration makes integration economically attractive for an increasing number of systems. Also, the rapid succession of generations of a single product increases the pressure on design time. The ability to integrate systems on silicon effectively, efficiently, and quickly has thus become a key factor in the global competition in both consumer and professional electronic products.

This book pursues a programming approach to the design of digital VLSI circuits. In such an approach the VLSI-system designer constructs a program in a suitable high-level programming language. When he is satisfied with his program, the designer invokes a so-called silicon compiler which translates this program into a VLSI-circuit layout.

The choice of the programming language is a crucial one, for it largely determines the application area, the convenience of design, and the efficiency of the compiled circuits. A good VLSI-programming language.

1. 0. is general purpose in that it allows the description of all digital functions;

2. 1. encourages the systematic and efficient design of programs by abstracting from circuit, geometry and technology details;

3. 2. is suitable for automatic translation into efficient VLSI circuits and test patterns.

Below follows a motivation for these requirements.

1. 0. A wide range of applications is required to justify the investment in tools and training.

2. 1. A major gain in design productivity can be expected by designing in a powerful highlevel language. Furthermore, system designers do not need to resort to VLSI specialists. Systematic design methods, supported by mathematical reasoning, are required to deal with the overwhelming complexity involved in the design of VLSI systems.

3. 2. Automatic translation to VLSI circuits avoids the introduction of errors at the lower abstraction levels. It also becomes attractive to design alternative programs and compare the translated circuits in costs (circuit area) and performance (speed and power).

Overview

Aims

This chapter describes a set of preliminary layout experiments using the system of three-dimensional abutment just described. The experiments are designed to configure the system and prepare the way for the experiments described in the next chapter. Specifically, the following questions are addressed:

• What are the important components of the merit functions?

• How should the components of the merit functions be weighted?

• What are the best algorithm control strategies?

• Is the system behaving sensibly?

The system is deliberately designed to operate in a highly flexible manner, and a primary goal of this first set of experiments is to determine those settings of the system parameters which produce the best layouts according to metrics which are discussed. This involves the postulation and evaluation of merit function components to control both placement and routing. In addition, the effect of different algorithm control strategies on layout is investigated, particularly the effect of the cluster shape and routing space controls. Finally, the system is used on circuits which are known to have optimal embeddings in the three-dimensional framework, and the results are used to indicate that the system exhibits appropriate behaviour and that the chosen system parameters are suitable.

Methods

The general experimental method used to determine the effect of some parameter or algorithm control is now described. First, a set of circuits for which layouts are constructed is defined. A variety of mainly random logic circuits is chosen in order to measure the layout system behaviour for a range of circuits. Each circuit is described in terms of simple NAND gates.

The configuration file of the Qudos Layout Editor describes routable layers such as metal and polysilicon and via layers which describe the relationship between routable layers. For three-dimensional CMOS SOI design rules, a vertical connection is described by a metal layer with no contact overlap. The contact overlap will be provided on the planar metal layer to which the vertical metal layer connects. The structure of the layers is shown in Figure A.1. The layer ‘Dummy’ avoids a limitation of the system, and is introduced to maintain full design rule checking. The corresponding configuration file is included below.

Wiring schemes

Introduction

A number of limitations imposed by the technology of three-dimensional integration have been mentioned. These limitations restrict the total number of transistors and the number of layers in which transistors can be constructed. However, for a given number of layers the topology of circuit layout is most profoundly affected by the availability and quality of wiring both within and between the layers.

For the layout problem, the distribution of wiring is determined by the edges in the physical layout graph, which is the initially empty spatial grid in which edges are wires and vertices are transistors or gates. The logical circuit graph specifies the structural connectivity of the circuit in terms of nodes and signals. Since layout consists of embedding the logical circuit graph into the physical layout graph, the pattern of edges in the physical graph has an effect on the compactness of the embedding. Contact and wiring techniques are now discussed.

Contact techniques

A range of contact techniques are available for three-dimensional structures, providing direct connection between diffusion, gate and wiring regions. Conventional contact methods which are used for connections within a single layer of transistors can be applied to create direct connections between layers of transistors. With the butting contact, regions are connected by contact with the wiring material which is particularly useful when the signal connected is required elsewhere in the circuit. In particular, connection can be formed between the gate and diffusion regions of a single transistor (Figure 4.1(a)), or a pair of stacked transistors (Figure 4.1(b)) [Kawamura 83].

Review

Aims

This dissertation has presented an investigation into three-dimensional integrated circuit layout and cell design. The primary goal of the investigation was to discover the potential benefits of such layout, and to determine whether those benefits justify the considerably more complex and costly techniques of fabrication which are involved.

Similar questions for other difficult fabrication techniques are more readily answered. The cost of techniques used to make smaller transistors is constantly being justified by the denser, faster and more highly integrated circuits and systems which result. It is also the case that such technology does not introduce any fundamentally new layout problems. A more difficult question to answer concerns the value of wafer-scale integration. This is because the benefits are clouded by yield problems, and new layout and fabrication methodologies must be introduced to achieve fault or failure tolerance. The best methods are still to be determined.

The value of three-dimensional integration is a yet more difficult question. The technological difficulties are as apparent as they are abundant, and include yield degradation and thermal stresses during fabrication and heat dissipation and crosstalk during circuit operation. However, the nature of the benefit is not clear. It has been speculated that three-dimensional circuits might be denser and faster, having shorter wiring and offering greater connection capabilities. These benefits are expected because of the inherently richer connection topology which the three-dimensional arrangement of devices offers. Little has been done and less has been published about such speculation.

Preliminary research

As with any new topic of such complexity, an investigation into three-dimensional integrated circuit layout is open-ended.