The adjective “nonlinear” will be used inclusively by taking “linear” to be a special case of “nonlinear.” As promised, we present in this chapter two different theories for nonlinear infinite networks. The first one is due to Dolezal and is very general in scope – except that it is restricted to 0-networks. It is an infinite-dimensional extension of the fundamental theory for scalar, finite, linear networks [67], [115], [127]. In particular, it examines nonlinear operator networks, whose voltages and currents are members of a Hilbert space ℋ; in fact, infinite networks whose parameters can be nonlinear, multivalued mappings restricted perhaps to subsets of ℋ are encompassed. As a result, virtually all the different kinds of parameters encountered in circuit theory – resistors, inductors, capacitors, gyrators, transformers, diodes, transistors, and so forth – are allowed. However, there is a price to be paid for such generality: Its existence and uniqueness theorems are more conceptual than applicable, because their hypotheses may not be verifiable for particular infinite networks. (In the absence of coupling between branches, the theory is easy enough to apply; see Corollary 4.1-7 below.) Nonetheless, with regard to the kinds of parameters encompassed, this is the most powerful theory of infinite networks presently available. Dolezal has given a thorough exposition of it in his two books [40], [41]. However, since no book on infinite electrical networks would be complete without some coverage of Doleza's work, we shall present a simplified version of his theory.

The purposes of this initial chapter are to present some basic definitions about infinite electrical networks, to show by examples that their behaviors can be quite different from that of finite networks, and to indicate how they approximately represent various partial differential equations in infinite domains. Finally, we explain how the transient responses of linear RLC networks can be derived from the theory of purely resistive networks; this is of interest because most of the results of this book are established in the context of resistive networks.

Notations and Terminology

Let us start by reviewing some symbols and phraseology so as to dispel possible ambiguities in our subsequent discussions. We follow customary usage; hence, this section may be skipped and referred to only if the need arises. Also, an Index of Symbols is appended for the more commonly occurring notations in this book; it cites the pages on which they are defined.

Let X be a set. X is called denumerably infinite or just denumerable if its members can be placed in a one-to-one correspondence with all the natural numbers: 0, 1, 2,. … X is called countable if it is either finite or denumerable. In this book the set of branches of any network will always be countable.

The notation {x ∈ X: P(x)}, or simply {x: P(x)} if X is understood, denotes the set of all x ∈ X for which the proposition P(x) concerning x is true.

Overview

Aims

This chapter describes a set of preliminary layout experiments using the system of three-dimensional abutment just described. The experiments are designed to configure the system and prepare the way for the experiments described in the next chapter. Specifically, the following questions are addressed:

• What are the important components of the merit functions?

• How should the components of the merit functions be weighted?

• What are the best algorithm control strategies?

• Is the system behaving sensibly?

The system is deliberately designed to operate in a highly flexible manner, and a primary goal of this first set of experiments is to determine those settings of the system parameters which produce the best layouts according to metrics which are discussed. This involves the postulation and evaluation of merit function components to control both placement and routing. In addition, the effect of different algorithm control strategies on layout is investigated, particularly the effect of the cluster shape and routing space controls. Finally, the system is used on circuits which are known to have optimal embeddings in the three-dimensional framework, and the results are used to indicate that the system exhibits appropriate behaviour and that the chosen system parameters are suitable.

Methods

The general experimental method used to determine the effect of some parameter or algorithm control is now described. First, a set of circuits for which layouts are constructed is defined. A variety of mainly random logic circuits is chosen in order to measure the layout system behaviour for a range of circuits. Each circuit is described in terms of simple NAND gates.

The configuration file of the Qudos Layout Editor describes routable layers such as metal and polysilicon and via layers which describe the relationship between routable layers. For three-dimensional CMOS SOI design rules, a vertical connection is described by a metal layer with no contact overlap. The contact overlap will be provided on the planar metal layer to which the vertical metal layer connects. The structure of the layers is shown in Figure A.1. The layer ‘Dummy’ avoids a limitation of the system, and is introduced to maintain full design rule checking. The corresponding configuration file is included below.

Wiring schemes

Introduction

A number of limitations imposed by the technology of three-dimensional integration have been mentioned. These limitations restrict the total number of transistors and the number of layers in which transistors can be constructed. However, for a given number of layers the topology of circuit layout is most profoundly affected by the availability and quality of wiring both within and between the layers.

For the layout problem, the distribution of wiring is determined by the edges in the physical layout graph, which is the initially empty spatial grid in which edges are wires and vertices are transistors or gates. The logical circuit graph specifies the structural connectivity of the circuit in terms of nodes and signals. Since layout consists of embedding the logical circuit graph into the physical layout graph, the pattern of edges in the physical graph has an effect on the compactness of the embedding. Contact and wiring techniques are now discussed.

Contact techniques

A range of contact techniques are available for three-dimensional structures, providing direct connection between diffusion, gate and wiring regions. Conventional contact methods which are used for connections within a single layer of transistors can be applied to create direct connections between layers of transistors. With the butting contact, regions are connected by contact with the wiring material which is particularly useful when the signal connected is required elsewhere in the circuit. In particular, connection can be formed between the gate and diffusion regions of a single transistor (Figure 4.1(a)), or a pair of stacked transistors (Figure 4.1(b)) [Kawamura 83].

Review

Aims

This dissertation has presented an investigation into three-dimensional integrated circuit layout and cell design. The primary goal of the investigation was to discover the potential benefits of such layout, and to determine whether those benefits justify the considerably more complex and costly techniques of fabrication which are involved.

Similar questions for other difficult fabrication techniques are more readily answered. The cost of techniques used to make smaller transistors is constantly being justified by the denser, faster and more highly integrated circuits and systems which result. It is also the case that such technology does not introduce any fundamentally new layout problems. A more difficult question to answer concerns the value of wafer-scale integration. This is because the benefits are clouded by yield problems, and new layout and fabrication methodologies must be introduced to achieve fault or failure tolerance. The best methods are still to be determined.

The value of three-dimensional integration is a yet more difficult question. The technological difficulties are as apparent as they are abundant, and include yield degradation and thermal stresses during fabrication and heat dissipation and crosstalk during circuit operation. However, the nature of the benefit is not clear. It has been speculated that three-dimensional circuits might be denser and faster, having shorter wiring and offering greater connection capabilities. These benefits are expected because of the inherently richer connection topology which the three-dimensional arrangement of devices offers. Little has been done and less has been published about such speculation.

Preliminary research

As with any new topic of such complexity, an investigation into three-dimensional integrated circuit layout is open-ended.