Asynchronous sequential circuits have state that is not synchronized with a clock. Like the synchronous sequential circuits we have studied up to this point, they are realized by adding state feedback to combinational logic that implements a next-state function. Unlike synchronous circuits, the state variables of an asynchronous sequential circuit may change at any point in time. This asynchronous state update – from next state to current state – complicates the design process. We must be concerned with hazards in the next-state function, since a momentary glitch may result in an incorrect final state. We must also be concerned with races between state variables on transitions between states whose encodings differ in more than one variable.

In this chapter we look at the fundamentals of asynchronous sequential circuits. We start by showing how to analyze combinational logic with feedback by drawing a flow table. The flow table shows us which states are stable, which are transient, and which are oscillatory.We then show how to synthesize an asynchronous circuit from a specification by first writing a flow table and then reducing the flow table to logic equations. We see that state assignment is quite critical for asynchronous sequential machines, since it determines when a potential race may occur. We show that some races can be eliminated by introducing transient states.

After the introduction given in this chapter, we continue our discussion of asynchronous circuits in Chapter 27 by looking at latches and flip-flops as examples of asynchronous circuits.

System-level timing is generally driven by the flow of information through the system. Because this information flows through the interfaces between modules, system timing is tightly tied to interface specification. Timing is determined by how modules sequence information over these interfaces. In this chapter we will discuss interface timing and illustrate how the operation of the overall system is sequenced via these interfaces, drawing on the examples introduced in Chapter 21.

How fast will an FSM run? Could making our logic too fast cause our FSM to fail? In this chapter, we will see how to answer these questions by analyzing the timing of our finite-state machines and the flip-flops used to build them.

Finite-state machines are governed by two timing constraints – a maximum delay constraint and a minimum delay constraint. The maximum speed at which we can operate an FSM depends on two flip-flop parameters (the setup time and propagation delay) along with the maximum propagation delay of the next-state logic. On the other hand, the minimum delay constraint depends on the other two flip-flop parameters (hold time and contamination delay) and the minimum contamination delay of the next-state logic. We will see that if the minimum delay constraint is not met, our FSM may fail to operate at any clock speed due to hold-time violations. Clock skew, the delay between the clocks arriving at different flip-flops, affects both maximum and minimum delay constraints.

A pipeline is a sequence of modules, called stages, that each perform part of an overall task. Each stage is like a station along an assembly line – it performs a part of the overall assembly and passes the partial result to the next stage. By passing the incomplete task down the pipeline, each stage is able to start work on a new task before waiting for the overall task to be completed. Thus, a pipeline may be able to perform more tasks per unit time (i.e., it has greater throughput) than a single module that performs the whole task from start to finish.

The throughput, or work done per unit time, of a pipeline is that of the worst stage. Designers must load balance pipelines to avoid idling and wasting resources. Stages that take a variable latency can stall all upstream stages to prevent data propagating down the pipeline. Queues can be used to make a pipeline elastic and tolerate latency variance better than global stall signals.

In this appendix we provide a summary of the VHDL syntax employed in this book. Before using this appendix you should first have read the introductions to VHDL in Section 1.5 and Section 3.6. In addition to this appendix you may find the subject index at the end of this book helpful when looking for information about specific VHDL syntax features. Excellent references documenting the complete VHDL language can be found elsewhere [3, 55]. However, due to the complexity of the VHDL language such references tend to lack detailed discussion of hardware design topics. An abridged summary of the key aspects of VHDL syntax, such as that found in this appendix, can be very helpful when learning hardware design.

Implementing the next-state and output logic of a finite-state machine using a memory array gives a flexible way of realizing an FSM. The function of the FSM can be altered by changing the contents of the memory. We refer to the contents of the memory array as microcode, and a machine realized in this manner is called a microcoded FSM. Each word of the memory array determines the behavior of the machine for a particular state and input combination, and is referred to as a microinstruction.

We can reduce the required size of a microcode memory by augmenting the memory with special logic to compute the next state, and by selectively updating infrequently changing outputs. A single microinstruction can be provided for each state, rather than one for each state × input combination, by adding an instruction sequencer and a branch microinstruction to cause changes in control flow. Bits of the microinstruction can be shared by different functions by defining different microinstruction types for control, output, and other functions.

In this chapter we will see how to build logic circuits (gates) using complementary metal– oxide–semiconductor (CMOS) transistors. We start in Section 4.1 by examining how logic functions can be realized using switches. A series combination of switches performs an AND function while a parallel combination of switches performs an OR function. We can build up more complex switch-logic functions by building more complex series–parallel switch networks.

In Section 4.2 we present a very simple switch-level model of an MOS transistor. CMOS transistors come in two flavors: NMOS and PMOS. For purposes of analyzing the function of logic circuits, we consider an NMOS transistor to be a switch that is closed when its gate is a logic “1” and that passes only a logic “0.” A PMOS transistor is complementary – it is a switch that is closed when its gate is a logic “0” and that passes only a logic “1.” To model the delay and power of logic circuits (which we defer to Chapter 5), we add a resistance and a capacitance to our basic switch. This switch-level model is much simpler than the models used for MOS circuit design, but is perfectly adequate to analyze the functionality and performance of digital logic circuits.

Using our switch-level model, we see how to build gate circuits in Section 4.3 by building a pull-down network of NMOS transistors and a complementary pull-up network of PMOS transistors. A NAND gate, for example, is realized with a series pull-down network of NMOS transistors and a parallel pull-up network of PMOS transistors.

Before we dive into the technical details of digital system design, it is useful to take a high-level look at the way systems are designed in industry today. This will allow us to put the design techniques we learn in subsequent chapters into the proper context. This chapter examines four aspects of contemporary digital system design practice: the design process, implementation technology, computer-aided design tools, and technology scaling.

We start in Section 2.1 by describing the design process – how a design starts with a specification and proceeds through the phases of concept development, feasibility studies, detailed design, and verification. Except for the last few steps, most of the design work is done using English-language documents. A key aspect of any design process is a systematic – and usually quantitative – process of managing technical risk.

Digital designs are implemented on very-large-scale integrated (VLSI) circuits (often called chips) and packaged on printed-circuit boards (PCBs). Section 2.2 discusses the capabilities of contemporary implementation technology.

The design of highly complex VLSI chips and boards is made possible by sophisticated computer-aided design (CAD) tools. These tools, described in Section 2.3, amplify the capability of the designer by performing much of the work associated with capturing a design, synthesizing the logic and physical layout, and verifying that the design is both functionally correct and meets timing.

Approximately every two years, the number of transistors that can be economically fabricated on an integrated-circuit chip doubles. We discuss this growth rate, known as Moore's law, and its implications for digital systems design in Section 2.4.

A relatively small number of modules, decoders, multiplexers, encoders, etc., are used repeatedly in digital designs. These building blocks are the idioms of modern digital design. Often, we design a module by composing a number of these building blocks to realize the desired function, rather than writing its truth table and directly synthesizing a logical implementation.

In the 1970s and 1980s most digital systems were built from small integrated circuits that each contained one of these building block functions. The popular 7400 series of TTL logic [106], for example, contained many multiplexers and decoders. During that period, the art of digital design largely consisted of selecting the right building blocks from the TTL databook and assembling them into modules. Today, with most logic implemented as ASICs or FPGAs, we are not constrained by what building blocks are available in the TTL databook. However, the basic building blocks are still quite useful elements from which to build a system.

In Chapter 14 we saw how a finite-state machine can be synthesized from a state diagram by writing down a table for the next-state function and synthesizing the logic that realizes this table. For many sequential functions, however, the next-state function can be more simply described by an expression rather than by a table. Such functions are more efficiently described and realized as datapaths, where the next state is computed as a logical function, often involving arithmetic circuits, multiplexers, and other building block circuits.

What happens when we violate the setup- and hold-time constraints of a flip-flop? Until now, we have considered only the normal behavior of a flip-flop when these constraints are satisfied. In this chapter we investigate the abnormal behavior that occurs when we violate these constraints. We will see that violating setup and hold times may result in the flip-flop entering a metastable state in which its state variable is neither a 1 nor a 0. It may stay in this metastable state for an indefinite amount of time before arriving at one of the two stable states (0 or 1). This synchronization failure can lead to serious problems in digital systems.

To stretch an analogy, flip-flops are a lot like people. If you treat them well, they will behave well. If you mistreat them, they behave poorly. In the case of flip-flops, you treat them well by observing their setup and hold constraints. As long as they are well treated, flip-flops will function properly, never missing a bit. If, however, you mistreat your flip-flop by violating the setup and hold constraints, it may react by misbehaving – staying indefinitely in a metastable state. This chapter explores what happens when these good flip-flops go bad.

In this chapter we work through several examples of combinational circuits to reinforce the concepts in the preceding chapters. A multiple-of-3 circuit is another example of an iterative circuit. The tomorrow circuit from Section 1.4 is an example of a counter circuit with subcircuits for modularity. A priority arbiter is an example of a building-block circuit – built using design entities described in preceding chapters. Finally, a circuit designed to play tic-tac-toe gives a complex example combining many concepts.

The specification for a digital system typically includes not only its function, but also the delay and power (or energy) of the system. For example, a specification for an adder describes (i) the function, that the output is to be the sum of the two inputs; (ii) the delay, that the output must be valid within 1 ns after the inputs are stable; and (iii) its energy, that each add consumes no more than 2 pJ. In this chapter we shall derive simple methods to estimate the delay and power of CMOS logic circuits.

Digital systems are pervasive in modern society. Some uses of digital technology are obvious – such as a personal computer or a network switch. However, there are also many other applications of digital technology. When you speak on the phone, in almost all cases your voice is being digitized and transmitted via digital communications equipment. When you listen to an audio file, the music, recorded in digital form, is processed by digital logic to correct errors and improve the audio quality. When you watch TV, the image is transmitted in a digital format and processed by digital electronics. If you have a DVR (digital video recorder) you are recording video in digital form. DVDs are compressed digital video recordings. When you play a DVD or stream a movie, you are digitally decompressing and processing the video. Most communication radios, such as cell phones and wireless networks, use digital signal processing to implement their modems. The list goes on.

Most modern electronics uses analog circuitry only at the edge – to interface to a physical sensor or actuator. As quickly as possible, signals from a sensor (e.g., a microphone) are converted into digital form. All real processing, storage, and transmission of information is done digitally. The signals are converted back to analog form only at the output – to drive an actuator (e.g., a speaker) or control other analog systems.

Not so long ago, the world was not as digital. In the 1960s digital logic was found only in expensive computer systems and a few other niche applications. All TVs, radios, music recordings, and telephones were analog.

The shift to digital was enabled by the scaling of integrated circuits. As integrated circuits became more complex, more sophisticated signal processing became possible. Complex techniques such as modulation, error correction, and compression were not feasible in analog technology. Only digital logic, with its ability to perform computations without accumulating noise and its ability to represent signals with arbitrary precision, could implement these signal processing algorithms.

In this book we will look at how the digital systems that form such a large part of our lives function and how they are designed.

This chapter gives some additional examples of sequential circuits. We start with a simple FSM that reduces the number of 1s on its input by a factor of 3 to review how to draw a state diagram from a specification and how to implement a simple FSM in VHDL. We then implement an SOS detector to review factoring of state machines. Next, we revisit our tic-tactoe game from Section 9.4 and build a datapath sequential circuit that plays a game against itself using the combinational move generator we previously developed. We illustrate the use of table-driven sequential circuits and composing circuits from sequential building blocks like counters and shift registers by building a Huffman encoder and decoder. The encoder uses table lookup along with a counter and shift register, while the decoder traverses a tree data structure stored in a table.