Silicon integrated circuits (ICs) are pervasive in our world, and the global semiconductor industry today exceeds $500 billion in annual sales. The devices and chips this industry produces support global industries, including consumer electronics, transportation, avionics and many others, that collectively represent a major part of global markets. Devices and chips built with other semiconductor materials such as GaAs, SiC and GaN provide critical components for specific application areas, including high-frequency communications systems, solid-state lighting and power management. It is not incorrect to say that the technical foundation of our modern world is based on semiconductors. The critical role that chips play has led to global competition to design, fabricate and build into advanced systems these remarkable components. Their importance to our world is unlikely to change in the foreseeable future.

In this chapter, we discuss the fabrication of a modern complementary metal-oxide–semiconductor (CMOS) integrated circuit using the individual process steps that are combined in a complete process flow sequence to make the chips. Such an ordered process flow from the sandbox of tools available in different combinations would be used to make any kind of device, such as a biosensor, a microfluidic device or a micro-electromechanical systems (MEMS) device. The wafer’s past history and the future process steps can greatly influence how one chooses to order the individual steps. For example, high-temperature steps at the end of a process could disturb delicate doping profiles introduced early in the process. For this reason, we believe it is worth understanding the choices made in assembling a modern CMOS process flow. Seeing the “big picture” of a complete process flow should also help to put the individual process steps we discuss in subsequent chapters into perspective.

One of the main challenges in designing a front-end process for building a device is accurate control of the placement of the active doping regions. Understanding and controlling diffusion and annealing behavior are essential to obtaining the desired electrical characteristics. Consider a cross-section of a state-of-the-art MOS transistor and imagine what happens when it gets scaled down to smaller dimensions (Figure 7.1). In “ideal” or Dennard scaling, as described in Chapter 1, everything shrinks down linearly from one generation to the next. This means that not only do the lateral dimensions scale, but the vertical dimensions, such as the deep source/drain contacting junctions and the shallower tip or extension junctions, also scale. This maintains the same electric field patterns (assuming the operating voltage also scales proportionally). With the same ℰ-field patterns, the device operates in the same manner as before, except that the shorter channel length allows for faster switching speeds [1].

Ion implantation has been the dominant doping technique for silicon integrated circuits (ICs) and most other semiconductors for the past 45 years. It is expected to retain this position of dominance for the foreseeable future. In this process, dopant ions are accelerated to 0.1–1000 keV of energy and smashed into a crystalline semiconductor substrate, creating a cascade of damage that may displace hundreds or thousands of lattice atoms for each implanted ion. In this chapter, we will seek to understand how such an energetic and violent technique has become the dominant and preferred method of doping semiconductor wafers in manufacturing. At first glance, it seems that the technique would not be of much use in the precise art of fabricating integrated circuits. Indeed, although the original patent for ion implantation was issued to William Shockley in 1954, it was not until the late 1970s that ion implantation was used in manufacturing.

If workers from one of today’s multi-billion-dollar integrated circuit (IC) manufacturing plants were suddenly transported to a 1960s semiconductor plant, they would likely be amazed that chips could be successfully manufactured in such a place. Such factories were “dirty” by today’s standards, and wafer cleaning procedures were poorly understood. Of course, chips were manufacturable even in those days, but they were very small and contained very few components by today’s standards. Since defects on a chip tend to reduce yields (fraction of good chips on a wafer) exponentially as chip size increases, small chips can be manufactured with a yield greater than zero even in quite dirty environments. However, all of the progress that has been made in the past six decades in shrinking device sizes and designing very complex chips would have been for naught if similar advances had not been made in manufacturing capability, especially in defect density.

The primary task of electrostatics is to find the electric field of a given stationary charge distribution. In principle, this purpose is accomplished by Coulomb’s law, in the form of Eq. 2.8:

The fundamental problem electrodynamics hopes to solve is this (Fig. 2.1): We have some electric charges, $q_1,q_2,q_3,\dots$ (call them source charges); what force do they exert on another charge, $Q$ (call it the test charge)? The positions of the source charges are given (as functions of time); the trajectory of the test particle is to be calculated.

Remember the basic problem of classical electrodynamics: we have a collection of charges $q_1,q_2,q_3,\dots$ (the “source” charges), and we want to calculate the force they exert on some other charge $Q$ (the “test” charge – Fig. 2.1). According to the principle of superposition, it is sufficient to find the force of a single source charge – the total is then the vector sum of all the individual forces.