INTRODUCTION

The modern microwave diode owes its existence to the demands of military radar during the Second World War. Vacuum tubes of the time were simply unable to operate in the multi-GHz radar frequency bands. Fortunately, the seeds of a breakthrough had been planted in the mid-1930s by Bell Labs scientist George C. South worth during his early work with cylindrical waveguides. Proving the old adage that “necessity is the mother of invention,” an inspired bit of thinking by his colleague, Russell Ohl, led him to try out crystal detectors (then nearly obsolete) as power sensors, hoping that the low capacitance associated with point contacts would permit operation at the high frequencies he was using (within an octave of 1 GHz). Promising results of tests on silicon confirmed that such diodes do indeed succeed where vacuum tubes fail. A crash development program by the MIT Radiation Laboratory and others successfully delivered reliable point-contact silicon diodes capable of operating at frequencies in excess of 30 GHz by the end of the war.

In this chapter, we examine diodes of this type. However, we also broaden the term “diode” to include many other two-terminal semiconductor elements that find use in microwave circuits. So, in addition to ordinary junction and Schottky diodes, we'll consider varactors (parametric diode), tunnel diodes (including backward diodes), PIN diodes, noise diodes, snap-off (step recovery) diodes, Gunn diodes, MIM diodes, and IMPATT diodes.

INTRODUCTION

In this chapter we examine the properties of passive components commonly used in RF work. Because parasitic effects can easily dominate behavior at gigahertz frequencies, our focus is on the development of simple analytical models for parasitic inductance and capacitance of various discrete components.

INTERCONNECT AT RADIO FREQUENCIES: SKIN EFFECT

At low frequencies, the properties of interconnect we care about most are resistivity, current-handling ability, and perhaps capacitance. As frequency increases, we find that inductance might become important. Furthermore, we invariably discover that the resistance increases owing to the skin effect alluded to in Chapter 5.

Skin effect is usually described as the tendency of current to flow primarily on the surface (skin) of a conductor as frequency increases. Because the inner regions of the conductor are thus less effective at carrying current than at low frequencies, the useful cross-sectional area of a conductor is reduced, thereby producing a corresponding increase in resistance.

From that perfunctory and somewhat mysterious description, there is a risk of leaving the impression that all “skin” of a conductor will carry RF current equally well. To develop a deeper understanding of the phenomenon, we need to appreciate explicitly the role of the magnetic field in producing the skin effect. To do so qualitatively, let's consider a solid cylindrical conductor carrying a time-varying current, as depicted in Figure 6.1.

INTRODUCTION

The subject of filter design is so vast that we have to abandon all hope of doing justice to it in any subset of a textbook. Indeed, even though we have chosen to distribute this material over two chapters, the limited aim here is to focus on important qualitative ideas and practical information about filters – rather than attempting a comprehensive review of all possible filter types or supplying complete mathematical details of their underlying theory. For those interested in the rigor that we will tragically neglect, we will be sure to provide pointers to the relevant literature. And for those who would rather ignore the modest amount of rigor that we do provide, the reader is invited to skip directly to the end of this chapter for the tables that summarize the design of several common filter types in “cookbook” form.

Although our planar focus would normally imply a discussion limited to microstrip implementations, many such filters derive directly from lower-frequency lumped prototypes. Because so many key concepts may be understood by studying those prototypes, we will follow a roughly historical path and begin with a discussion of lumped filter design. It is definitely the case that certain fundamental insights are universal, and it is these that we will endeavor to emphasize in this chapter, despite differences in implementation details between lumped and distributed realizations. We consider only passive filters here, partly to limit the length of the chapter to something manageable.

Motivation

Modern transceivers for wireless communication consist of many building blocks, including low-noise amplifiers, mixers, frequency synthesizers, filters, variable-gain amplifiers, power amplifiers, and even digital signal processing (DSP) chips. Each of these building blocks has a different specification, imposes different constraints, and requires different design considerations and optimization. As a result, wireless transceivers have been exclusively implemented using hybrid technologies, mainly GaAs for low noise and high speed, bipolar for high power, passive devices for high selectivity and CMOS for DSP at the baseband. While taking advantage of the best in each technology, this hybrid combination unfortunately requires multi-chip modules and off-chip components, which not only are costly and bulky, but also consume a lot of power.

However, recent development and advance scaling of deep-submicron CMOS technologies have made it more feasible and more promising to implement a single-chip CMOS wireless transceiver. This single-chip integration is particularly attractive for its potential in achieving the highest possible level of integration and the best performance in terms of cost, size, weight, and power consumption.

Among the many design issues and considerations in single-chip CMOS integration is the aggressive scaling of the channel length. According to the Semiconductor Industry Association's roadmap in November 2001, the channel length will be scaled to be as small as 65 nm in 2007, as illustrated in Fig. 1.1.

Introduction

The impact of low-voltage design is degradation in speed, because of limited driving capability, and in signal-to-noise ratio (SNR), because of the reduced signal swing. In addition, for synthesizer designs, a low supply voltage reduces the frequency tuning range and degrades the phase noise unless the current and power consumption are increased. Moreover, the design of prescalers and high-speed digital circuits becomes much more challenging because of the speed degradation of digital circuits with a low-voltage supply. This chapter discusses these design considerations and presents some of the design techniques required for critical building blocks in RF CMOS synthesizers as the supply voltage is lowered.

System considerations

The control voltage of the VCO in a synthesizer becomes limited under a low supply voltage. This results in a limited frequency tuning range with a given VCO gain. A larger VCO gain could be used to compensate for the degradation of the tuning range at the expense of the phase-noise and spurious-tone performance of the system. A high loop bandwidth helps to improve rejection of the VCO phase noise but sacrifices the spurious-tone suppression. In contrast, a small PLL loop bandwidth can provide larger spurious-tone suppression but results in less rejection of the VCO phase noise. On other hand, LC oscillators can achieve better phase noise than ring oscillators for a given power. As a consequence, a synthesizer using an LC oscillator with a small loop bandwidth can attain optimized performance in terms of noise and spurious suppression.

Introduction

Nowadays, many integrated circuits are operated in the multi-gigahertz range to increase their processing power and data bandwidth. High-speed clock generation is necessary for both RF systems and microprocessor systems. For high-frequency synchronous systems, the clock fluctuation needs to be minimized to prevent race conditions, to shorten the setup time and hold time requirements, and to increase the maximum possible operating speed of clocked systems.

Local oscillators (LOs), key elements in transceivers, are required to down-convert or up-convert RF signals while minimizing degradation of the signal-to-noise ratio (SNR). The LO signal is expected to be an ideal tone, which should be stable and clean and appear as a sharp impulse. Unfortunately, in practical situations, intrinsic noise from devices and noise from the surrounding environment make the LO signal fluctuate. As a result, the LO signal appears with sideband noise as a skirt centered around the impulse in the frequency domain. For wireless applications, this noise performance affects the SNR and is characterized by measuring the phase noise, which is defined as the ratio of the power of the signal at the desired frequency to the power of the signal at an offset frequency. For clocked system applications, jitter is normally used to characterize timing uncertainty of a clock signal in the time domain, which is defined as the deviation of the zero-crossing points from the ideal waveform.

In order to generate a high frequency and stable clock signal, frequency synthesis is necessary.

Introduction

Performing transistor-level transient simulation of frequency synthesizers normally takes a very long time. As a result, it is typically neither practical nor worthwhile to verify the transient performance of the synthesizers with simulations at the transistor level. Alternatively, carrying out system-level simulations or behavioral simulations can be quite important and critical in optimizing design parameters and in boosting up the efficiency and verification of a design. A suggested design procedure for PLLs is shown in Fig. 5.1. The first step is the specification definition, in which all the critical parameters are determined, including architecture, output frequency, input frequency, division ratio N, VCO gain KVCO, charge pump current ICP, and loop bandwidth BW. After defining the specification, mathematical models and behavioral models can be constructed for each building block, and for the whole synthesizer, to verify the stability. The issues and considerations of system simulations of RF frequency synthesizers are discussed in this chapter.

Linear model

The block diagram of a third-order synthesizer is shown in Fig. 5.2. The critical parameters to be defined first are the division ratios N1 and N2 as the synthesizer system. The division ratios are determined based on the relation between the input reference and the output frequencies. If a desired output clock frequency is to be 3.2 GHz, while the input clock frequency is 100 MHz, this leads to the division ratios N1 and N2 to be 1 and 32, respectively.

This chapter introduces the fractional-N synthesizer, which is also aimed at GSM applications with a supply voltage of 1.5 V. The synthesizer employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, a low-supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5 μm CMOS process, a fully integrated fractional synthesizer prototype with a third-order sigma–delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is around 1.0 mm2. The settling time is less than 250 μs, and the phase noise is better than −115 dBC/Hz at 600 kH3 offset.

Introduction

In monolithic phase-locked-loop (PLL) frequency synthesizer design, the phase noise performance of the synthesizer is degraded not only by the phase noise of the voltage-controlled oscillator (VCO) itself and the noise from the loop filter, but also by the substrate noise. Since the substrate is conductive, any noise generated from other circuits will couple through the substrate to the VCO and degrade the phase noise. This noise source is difficult to predict and cannot be prevented or reduced significantly even by increasing power consumption. Large separation from noise sources and guard rings can help reduce substrate coupling, but the effectiveness is quite limited in practice due to the compact layout for a small chip area.

Switching speed is limited in PLL-based synthesizers.

A frequency synthesizer by itself is a complicated system consisting of many building blocks connected in a feedback loop. Specifically, as shown in Fig. 2.7, these building blocks include a voltage-controlled oscillator (VCO), dividers, a phase-frequency detector, a charge pump, and a loop filter. Each of these building blocks affects the overall synthesizer's performance differently and thus have different design issues and criteria. This chapter will focus on reviewing and discussing these design considerations. In addition, design issues for passive components like inductors and varactors, which are critical for high-frequency VCOs and dividers, will also be presented.

Voltage-controlled oscillators (VCOs)

One of the most critical building blocks in any phase-locked loop or frequency synthesizer is the voltage-controlled oscillator. In general, the oscillator needs to operate at the highest frequency, and its phase noise is dominant in the whole system at frequency offsets beyond the synthesizer's loop bandwidth. In current CMOS technologies, both ring oscillators and LC-tank oscillators can be fully integrated on-chip (Lee, Kim and Lee, 1997; Momtaz et al., 2001), but both types have their own advantages and disadvantages. Depending on the specifications and applications, one may be more suitable than the other. The following sections will discuss and compare the design issues for the two types of VCOs.

Ring oscillators

Ring oscillators are typically easier to implement, and so are more desirable in standard CMOS technologies because it is not necessary to employ passive devices such as inductors and varactors.

A very low voltage synthesizer designed for WLAN is introduced in this chapter. Novel circuit designs discussed in Chapter 5 are demonstrated, such as for the VCO and programmable divider. The measured phase noise is −136 dBc/Hz at an offset of 20 MHz from the carrier, while the spurious tone is better than −80 dBc at the offset of the reference clock frequency. The synthesizer dissipates 27.5 mW from a single 1 V supply. The total core area occupies 1.03 mm2.

WLAN overview

IEEE 802.11a is a new standard aimed at high-speed wireless LAN communication systems. A high data rate of up to 54 Mbps can be offered between portable devices. It is designed for the 5 GHz frequency spectrum employing orthogonal frequency division multiplexing (OFDM) as its modulation scheme.

IEEE 802.11a is allocated a bandwidth of 300 MHz, which is separated into three bands with 100 MHz for each, according to different transmitting powers (Fig. 8.1). The three bands are the lower band, the middle band and the upper band. The lower band and middle band are specified for indoor communication, and the maximum transmit powers are 40 mW and 200 mW, respectively. The upper band is suited for outdoor use with a larger transmitting power of up to 800 mW. Each band contains four channels and each channel occupies 20 MHz bandwidth with 48 data sub-carriers, four pilot sub-carriers, and one nulled sub-carrier. Another 11 sub-carriers are discarded during signal processing (Agilent, 2003).