Hostname: page-component-848d4c4894-75dct Total loading time: 0 Render date: 2024-05-05T21:59:44.001Z Has data issue: false hasContentIssue false
  • English
  • Français

Design and layout strategies for integrated frequency synthesizers with high spectral purity

Published online by Cambridge University Press:  05 June 2017

Frank Herzel  and
Dietmar Kissinger
Frank Herzel*
Affiliation:
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
Dietmar Kissinger
Affiliation:
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany Technische Universität Berlin, Einsteinufer 17, 10587 Berlin, Germany
*
Corresponding author: F. Herzel Email: herzel@ihp-microelectronics.com
Get access Rights & Permissions [Opens in a new window]

Abstract

Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.

Keywords

Noise analysisRF front-endsFrequency synthesizer
Type
Tutorial and Review Paper
Information
International Journal of Microwave and Wireless Technologies , Volume 9 , Issue 9 , November 2017 , pp. 1791 - 1797
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2017 

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

[1] Pamarti, S.; Jansson, L.; Galton, I.: A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation. IEEE J. Solid-State Circuits, 39 (2004), 49–62.Google Scholar
[2] Pellerano, S.; Mukhopadhyay, R.; Ravi, A.; Laskar, J.; Palaskas, Y.: A 39.1-to-41.6 GHz ΔΣ fractional-N frequency synthesizer in 90 nm CMOS, in ISSCC Digest of Technical Papers, San Francisco, USA, 2008.Google Scholar
[3] Herzel, F. et al. : An integrated 18 GHz fractional-N PLL in SiGe BiCMOS technology for satellite communications, in IEEE Radio Frequency Integrated Circuits Symp. (RFIC), Boston, USA, 2009.CrossRefGoogle Scholar
[4] Osmany, S.A.; Herzel, F.; Scheytt, J.C.: Analysis and minimization of substrate spurs in fractional-N frequency synthesizers. Analog Integr. Circuits Signal Process., 74 (2013), 545–556. DOI: 10.1007/s10470-012-0002-x.Google Scholar
[5] Cressler, J.D.: SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications. IEEE Trans. Microw. Theory Tech., 46 (1998), 572–589.CrossRefGoogle Scholar
[6] Lacaita, A.; Levantino, S.; Samori, C.: Integrated Frequency Synthesizers for Wireless Systems, Cambridge University Press, Cambridge, 2007.Google Scholar
[7] Miller, B.: A multiple modulator fractional divider. IEEE Trans. Instrum. Measurements, 40 (1991), 578–583.Google Scholar
[8] Riley, T.A.D.; Filiol, N.M.; Du, Q.; Kostamovaara, J.: Techniques for in-band phase noise reduction in ΔΣ synthesizers. IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., 50 (2003), 794–803.Google Scholar
[9] De Muer, B.; Steyaert, M.S.J.: On the analysis of ΔΣ fractional-N frequency synthesizers. IEEE Trans. Circuits Systems II: Analog Digit. Signal Process., 50 (2003), 784–793.Google Scholar
[10] Heyer, H.-V. et al. : Wide frequency range fractional-N synthesizer with improved phase noise for flexible payloads, in Proc. of 2nd ESA Workshop on Advanced Telecom Payloads, Noordwijk, The Netherlands, 2012.Google Scholar
[11] Wan, K.J.; Swaminathan, A.; Galton, I.: Spurios tone suppression techniques applied to a wide-bandwidth 2.4 GHz fractional-N PLL. IEEE J. Solid-State Circuits, 43 (2008), 2787–2797.Google Scholar
[12] Brennan, P.V.; Wang, H.; Jian, D.; Radmore, P.M.: A new mechanism producing discrete spurious components in fractional-N frequency synthesizers. IEEE Trans. Circuits Syst. I: Regular Papers, 55 (2008), 1279–1288.Google Scholar
[13] Herzel, F.; Osmany, S.A.; Scheytt, J.C.: Analytical phase-noise modeling and charge pump optimization for fractional-N PLLs. IEEE Trans. Circuits Syst. I: Regular Papers, 57 (2010), 1914–1924.CrossRefGoogle Scholar
[14] Chien, H.-M. et al. : A 4 GHz fractional-N synthesizer for IEEE 802.11a, in Symp. on VLSI Circuits Digest of Technical Papers, Honolulu, USA, 2004.Google Scholar
[15] Kucharski, M.; Herzel, F.; Kissinger, D.: Time-domain simulation of quantization noise mixing and charge pump device noise in fractional-N PLLs, in Proc. of the 13th IEEE Int. New Circuits and Systems Conf. (NEWCAS), Grenoble, France, 2015.CrossRefGoogle Scholar
[16] Herzel, F.; Razavi, B.: A study on oscillator jitter due to supply and substrate noise. IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., 46 (1999), 56–62.Google Scholar
[17] Hegazi, E.; Rael, J.; Abidi, A.: The Designer's Guide to High-Purity Oscillators, Springer, New York, 2004.Google Scholar
[18] Hu, K., Osmany, S.A.; Scheytt, J.C.; Herzel, F.: An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance. Analog Integr. Circuits Signal Process., 67 (2011), 319–330. DOI: 10.1007/s10470-011-9622-9.Google Scholar
[19] Ng, H.J.; Fischer, A.; Feger, R.; Stuhlberger, R.; Maurer, L.; Stelzer, A.: A DLL-supported, low phase noise fractional-N PLL with a wideband VCO and a highly linear frequency ramp generator for FMCW radars. IEEE Trans. Circuits Syst. I: Regular Papers, 60 (2013), 3289–3302.CrossRefGoogle Scholar
[20] Kucharski, M.; Herzel, F.: Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs. Adv. Radio Sci., 13 (2015), 133–139.Google Scholar
[21] Herzel, F.; Borngraeber, J.; Ergintav, A.; Kissinger, D.: A 17 GHz programmable frequency divider for space applications in a 130 nm SiGe technology, in IEEE Bipolar/BiCMOS and Technology Meeting (BCTM), Boston, MA, USA, 2015.Google Scholar
[22] Ruecker, H. et al. : A 0.13 SiGe BiCMOS technology featuring f T /f max of 240/330 GHz and gate delays below 3 ps. IEEE J. Solid-State Circuits, 45 (2010), 1678–1686.Google Scholar