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Fabrication process, experimental results, and application for an elemental level vertically intergrated circuit (ELVIC)

Published online by Cambridge University Press:  31 January 2011

Tadayoshi Enomoto
Tadayoshi Enomoto
Affiliation:
Ultra-LSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation, 4-1-1 Miyazaki, Miyamae-ku, Kawasaki-shi, Kanagawa-ken 213, Japan
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Abstract

A new double-layered stacked LSI fabrication process has been developed for the purpose of realizing short fabrication turn-around time, high fabrication yield, and high integration density. This process, which is named “Elemental Level Vertical Integrated Circuit (ELVIC)” technology, puts two conventionally made LSI chips face to face and bonds them by thermal compression. The process includes, in addition to the conventional LSI fabrication process, vertical interconnection (VI) formation in the upper and lower LSI layers, planarization of both upper and lower layer surfaces, and inter-level connections using pressure and heat. In the experimental version, about 52 000 10X10μm2 Au-on-Ti VIs were connected on a 5×5 mm2 chip. Each pair of mated VIs was measured and had a tensile strength of 4 mg · force. A two-layer, 31-stage inter-CMOS/bulk ring oscillator consisting of p-channel MOSFETs on the upper layer and n-channel MOSFETs on the lower layer has been built. Propagation delay time per stage is 1.86 ns at the supply voltage of 5 V. ELVIC technology can produce a variety of benefits such as high production yield, doubling integration density, latchup-free CMOS LSIs, radiation-damage-free LSIs, multifunction, and complete mixing of bipolar, CMOS, and GaAs technologies.

Type
Articles
Information
Journal of Materials Research , Volume 1 , Issue 4 , August 1986 , pp. 552 - 559
Copyright
Copyright © Materials Research Society 1986

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References

1Akiyama, S., Ogawa, S., Yoneda, M., Yoshii, N., and Terui, Y., “Multi-layer CMOS Device Fabrication on Laser Recrystallized Silicon Islands,” IEDM Digest of Technical Papers, pp. 352–355 (1983).CrossRefGoogle Scholar
2Nakano, M., “3-D SOI/CMOS” IEDM Digest of Technical Papers, pp. 729–795 (1984).Google Scholar
3Yasumoto, M., Hayama, H., and Enomoto, T., “Promising New Fabrication Process Developed for Stacked LSIs,” IEDM Digest of Tech- nical Papers, pp. 816–819 (1984).Google Scholar
4Enomoto, T., “Fabrication Process, Application and Future for an Elemental Level Vertically Integrated Circuit (ELVIC),” Final Program and Abstracts, Materials Research Society, 1985 Fall Meeting, Boston, p. 106 (Dec. 1985).CrossRefGoogle Scholar
5Kasahara, K., Isoda, Y., Moriyama, I., and Enomoto, T., “Vertically Integrated InGaAsP/InP LED on Si Device,” in Proceedings of the 1985 National Conference on Semiconductor Devices and Materials, Institute of Electronics and Communication Engineers of Japan, November, 1985, Vol. 1, Paper No. 283, p. 98.Google Scholar