The 20th century has seen considerable technological achievement that has had far-reaching consequences on the way people live and do business. The first half of the century saw remarkable developments in transportation with the automobile and the airplane and in communications with radio and television. These developments would not have been possible without associated advances in materials technology. The second half of the century has been characterized by the development of the computer (see the cover of this issue).

Nineteenth century futurists equated progress with scale. The bigger the better. One can only speculate on what these savants would say if introduced to what we currently call progress. Progress is now measured by how small you can make a device, how narrow you can make a conductor, and how many circuits you can fit onto the point of a pin (see Figure 1).

A modern integrated circuit (IC) is composed of 106 or more electronic devices. They are connected to form a circuit through the use of metallic films patterned into strips which function as wires to interconnect devices. These wires are usually simply referred to as interconnects. In an IC occupying the surface of a 1 cm2 Si chip, there can be 10 m of total interconnect length. This length is in the form of more than 106 line segments contacting pairs of devices and different segments of the circuit. This enormous number of wires is made possible by their small widths. Interconnect widths as small as 0.55 μm are currently used in commercial circuits, and circuits and processes leading to smaller and smaller widths are continuously in development.

During operation of an IC, interconnects carry current densities as high as 4 × 105 A/cm2. This should be compared with a current density of 102 A/cm2, the maximum allowed for house wiring. Thin-film conductors can carry these high current densities only because of the relatively good heat sinking provided by the Si substrate.

The problem of stress-induced voiding in the metal lines used for VLSI interconnections appeared about 10 years ago and was first reported in the literature in 1984. Some typical voids are shown in Figure 1. It is not entirely coincidental that the problem is of about the same age as the personal computer. The continuing advances in process technology that make possible the ever lower costs and improved performance of VLSI devices often have unexpected and troublesome side effects. Continuous attention to potential effects of process changes on the behavior of the materials comprising a VLSI chip is essential to avoid passing on problems to customers. The history of stress-induced voiding provides a good illustration.

The development of microelectronic miniaturization has taken an almost revolutionary course. For more than 20 years, important performance features have doubled every one to one and a half years on a per-chip level and, despite some recent economic worries, most people believe that we will see equally rapid progress for at least another 10 years. CMOS technology is making the fastest advances among the different microelectronic technologies and is pushing forward most powerfully. The acronym CMOS stands for Complementary Metal Oxide Semiconductor (chapter 8 in Reference 1) and means that two complementary types of transistor devices carry a current for complementary bias conditions. A device of this kind often used for switching purposes is drawn schematically in Figure 1. It uses a control electrode, called the gate, to switch a current flow from the terminal source to the terminal drain. The channel can be made conducting depending on the potential applied to the gate which is separated from the semiconductor by an insulating dielectric layer, namely amorphous SiO2. Control is via a field effect; for example, in one of the two complementary types of devices, a positive gate voltage can draw negatively charged electrons toward the interface, which causes conduction from the source to the drain through the otherwise blocked source and drain contacts.

Reliable long wavelength laser diodes emitting in the 1.30−1.55 μm regime with an expected operating life greater than 25 years for optical fiber communication applications are now fabricated using a combined heavy screening and accelerated aging process. For a given laser structure, the reliability of the devices depends intricately on both the crystalline perfection of the complex buried-heteroepitaxial semiconductor structures as well as the qualities of structures external to the semiconductor, such as electrical contact, dielectric coating, bonding, and packaging structures external to the semiconductor. The former (crystalline perfection) determines the intrinsic property of the laser, while the latter qualities (electrical contact, etc.) determine the contact resistance, parasitic capacitance, heating, and mechanical and thermal stresses to which a packaged laser device is subjected during operation. Since device heating and external stresses both degrade laser performance and accelerate permanent damage—through processes such as crystalline defect formation, current leakage path development, and doping profile redistribution—a reliable laser device, therefore, requires both a perfect semiconductor structure and also a high-quality external structure. Realistically, however, this may not be easily achievable, especially when a development program is limited in resource and time. Proper choice of the critical material issues in a development process becomes crucial to the success of the program.

In early electronic technologies, circuit components were attached to circuit boards by mechanical means. The electrical leads were either twisted together or mechanically interlocked to a board prior to soldering. The possibility of an unreliable solder joint causing any kind of circuit failure was remote. Interconnections were made intrinsic to the board by applying solder to increase electrical and thermal conductance. Technological advances and the need for high-density electronics have since eliminated the luxury of mechanical interlocks. Soldering in advanced applications, like surface mount technology (SMT), provides electrical, thermal, and mechanical interconnections between the board and its electrical components. In SMT, solder joints are the only mechanical features on the board and must hold components in place in a wide range of environments. The solder joints themselves are decreasing in size as increased chip functionality and clock frequencies become available. The failure of a single solder joint can render a device, or an entire electrical system, inoperable. Therefore, as insignificant and innocuous as they may seem, solder joints have become a critical aspect of electronic circuit reliability.

Electronics packaging has always accounted for about 50% of reliability shortcomings in electronics systems. Materials, processes, and geometries used in microelectronics packaging are quickly evolving to meet the commercial challenge for more reliable, lighter, smaller, cheaper devices, and lower power consumption. Amid the rapid evolution, methodology and metrology to measure package reliability and materials aging properties must be standardized to allow quantitative technology comparisons.

What Is Packaging?

For most purposes packaging can be thought of as everything involved in making an electronics system except the wafer fabrication. For example, all the design, fabrication, assembly, and finishing that goes into interconnecting the integrated circuits, discrete devices, resistors, and capacitors and then interfacing the system to the user is traditionally called “packaging.”