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Optimization of Flash Annealing Parameters to Achieve Ultra-Shallow Junctions for sub-45nm CMOS

Published online by Cambridge University Press:  01 February 2011

Pankaj Kalra ,
Prashant Majhi ,
Hsing-Huang Tseng ,
Raj Jammy  and
Tsu-Jae King Liu
Pankaj Kalra
Affiliation:
pk@eecs.berkeley.edu, University of California, Berkeley, EECS, 373 Cory Hall, Berkeley, CA, 94720, United States, 510-643-2558, 510-643-2636
Prashant Majhi
Affiliation:
prashant.majhi@sematech.org, SEMATECH, Austin, TX, 78741, United States
Hsing-Huang Tseng
Affiliation:
hsing-huang.tseng@sematech.org, SEMATECH, Austin, TX, 78741, United States
Raj Jammy
Affiliation:
raj.jammy@sematech.org, SEMATECH, Austin, TX, 78741, United States
Tsu-Jae King Liu
Affiliation:
tking@eecs.berkeley.edu, University of California, Berkeley, EECS, Berkeley, CA, 94720, United States
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Abstract

The use of millisecond annealing to meet ultra-shallow junction requirements for sub-45nm CMOS technologies is imperative. In this study, the effect of flash anneal parameters is presented. Reduced dopant diffusion and lower sheet resistance Rs is achieved for intermediate temperature Tint = 700°C (vs. 800°C). Significantly lower Rs is achieved with peak temperature Tpeak = 1300°C (vs. 1250°C). Multiple shots provide for lower Rs, albeit at the expense of increased dopant diffusion. Based on a simple quantitative model, an optimal flash anneal can achieve 82% dopant activation efficiency.

Keywords

Siannealingdiffusion
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1070: Symposium E – Doping Engineering for Front-End Processing , 2008 , 1070-E04-04
Copyright
Copyright © Materials Research Society 2008

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References

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