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Four-element LC-baluns for power matching arbitrary impedances

Published online by Cambridge University Press:  27 November 2024

Rasmus Alexander Jepsen
Affiliation:
Technical University of Denmark (DTU), Kongens Lyngby, Denmark
Jan Henrik Ardenkjær-Larsen
Affiliation:
Technical University of Denmark (DTU), Kongens Lyngby, Denmark
Vitaliy Zhurbenko*
Affiliation:
Technical University of Denmark (DTU), Kongens Lyngby, Denmark
*
Corresponding author: Vitaliy Zhurbenko; Email: vizh@dtu.dk
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Abstract

Six four-element balun topologies are introduced that enable complex impedance matching in addition to common-mode rejection. Design equations for these topologies are presented. Three of these networks are universal, while the other three are capable of performing only specific impedance transformations. Examples of these networks were designed and fabricated along with a traditional lattice balun network for an operating frequency of 300 MHz. These networks were verified through extensive electromagnetic simulations and by measuring the fabricated networks. The fabricated novel network examples were able to achieve common-mode rejection ratios above 20 dB, power wave reflection coefficients below −20 dB, and insertion losses of approximately 0.1 dB; these results were similar to or better than the performance of the fabricated traditional lattice balun. The design example networks also provided power matching and low insertion loss over a greater bandwidth compared to the fabricated traditional network. These networks will allow for the footprints of lumped-element balun circuitry to be reduced, which is particularly useful in integrated circuit design. These topologies are also expected to further increase radio-frequency (RF) circuit design flexibility by offering more alternative realizations.

Information

Type
Research Paper
Creative Commons
Creative Common License - CCCreative Common License - BY
This is an Open Access article, distributed under the terms of the Creative Commons Attribution licence (http://creativecommons.org/licenses/by/4.0), which permits unrestricted re-use, distribution and reproduction, provided the original article is properly cited.
Copyright
© The Author(s), 2024. Published by Cambridge University Press in association with The European Microwave Association.
Figure 0

Figure 1. (a) LC lattice balun extended to match complex impedances and (b) novel Yu network balun.

Figure 1

Figure 2. (a) Three-port and (b) two-port models of balun topologies.

Figure 2

Figure 3. Four-element balun topologies.

Figure 3

Table 1. Design equations for balun topologies

Figure 4

Table 2. Design equations for the Dipper, Yu, and Reverse Yu networks for $R_B = 4 R_U$

Figure 5

Figure 4. (a) Ideal traditional lattice balun and (b) implemented traditional lattice balun.

Figure 6

Figure 5. (a) Ideal Yu solution 2 balun and (b) implemented Yu solution 2 balun.

Figure 7

Figure 6. (a) Ideal extended Pi solution 2 balun and (b) implemented three-element balun.

Figure 8

Figure 7. Fabricated PCBs for the example (a) lattice, (b) Yu, and (c) three-element networks. Ports are annotated with their corresponding three-port port numbers. The dimensions of the lattice network PCB are 24.5 mm by 18.1 mm. The dimensions of the Yu network PCB are 20.9 mm by 17.9 mm. The dimensions of the three-element network PCB are 16.9 mm by 14.0 mm.

Figure 9

Figure 8. Measured and simulated common-mode rejection ratios of example balun networks.

Figure 10

Figure 9. Power wave reflection coefficient at the balanced port and insertion loss for the fabricated example (a) traditional lattice, (b) Yu, and (c) three-element networks.

Figure 11

Table A1. Conditions for each simulated test case

Figure 12

Figure A1. (a) CMRR, (b) power wave reflection coefficients, and (c) insertion loss for each network for the first test case at the design frequency.

Figure 13

Figure A2. (a) CMRR, (b) power wave reflection coefficients, and (c) insertion loss for each network for the second test case at the design frequency.

Figure 14

Figure A3. (a) CMRR, (b) power wave reflection coefficients, and (c) insertion loss for each network for the third test case at the design frequency.