Device description

Epitaxial layers

The two DHBT epitaxial layers were grown by metal-organic chemical vapour deposition (MOCVD) on 2-inch semi-insulating substrates. The two only differ for the sub-collector design: the first one features a 50 nm of heavily doped InP and 20 nm of lattice-matched GaInAs, which operates as the collector contact layer, whereas in the second one the InP is completely omitted and the GaInAs layer is thinned to 7.5 nm and made In-rich. The thermal conductivity of the GaInAs is lower when it is lattice-matched on InP, but increases for both Ga-rich and In-rich [Reference Adachi8]. In-rich composition has a higher electron mobility, which helps compensating for the increase in sheet resistance of the thinner layer [Reference Chattopadhyay, Sutradhar and Nag9]. The fraction of Indium in the layer was set to 62%, due to limits in the MOCVD growth.

The details of the two structures are reported in Tables 1 and 2. From now on, they will be labelled structure A for the thicker sub-collector and B for the thinner one.

Table 1.

Epitaxial structure A

Table 2.

Epitaxial structure B

Device fabrication

The fabrication process begins with the pattering in e-beam lithography of the emitter contact, followed by a metal deposition with an e-beam evaporator. The emitter mesa is partially etched and the “emitter-fin” of the emitter cathode is patterned and deposited. This addition to the emitter metal sets the distance between the emitter mesa side-wall and the yet to be deposited base metal, also called “base-access-distance”. At the same time, it also allows for the deposition of a thicker base metal. These two effects combined dramatically decrease the base resistance, thus boosting the RF-performances of the DHBT [Reference Arabhavi, Ciabattini, Hamzeloui, Flückiger, Saranovac, Han, Marti, Bonomo, Chaudary, Ostinelli and Bolognesi2].

Next, the emitter mesa etching is completed and the base metal deposited in a self-aligned fashion over the emitter metal. Then, the emitter mesa side-wall and the base-access-distance are passivated with aluminum oxide (AlOx). The base-collector mesa is etched and the collector contact deposited. The devices are isolated one from the other and planarized with Teflon Amorphous Fluoropolymer (TAF). GSG probing pads conclude the fabrication. Besides different etching times for the collector, there is no difference in the fabrication process of the transistors based on the two epitaxial structures. Details of the fabrication process can be found in [Reference Arabhavi, Ciabattini, Hamzeloui, Flückiger, Saranovac, Han, Marti, Bonomo, Chaudary, Ostinelli and Bolognesi2, Reference Bolognesi, Arabhavi, Hamzeloui and Fornari10]. Figure 1a and 1b show the FIB/SEM cross-section of the final transistors with the epitaxial structure A and B, respectively.

Figure 1.

FIB/SEM cross-section of the (0.25 × 10) µm² DHBT fabricated on the epitaxial structure A (a) and B (b). In (b) it can be seen how the separation between the base and the collector contacts is smaller, as highlighted by the arrows.

DC and RF measurements

Figure 2 reports the DC Gummel characteristics of a (0.25 × 10 µm²) single-finger common-emitter DHBT, with the open-base common-emitter breakdown voltage characteristics displayed in the insets for both epitaxial structures A and B. They both feature a DC gain β ≥ 25 and a BV _CEO ≥ 4.5 V. This confirms the excellent voltage-handling capabilities of this technology.

Figure 2.

Typical gummel characteristics of (0.25 × 10) µm² DHBT at V _CB = 0 v fabricated on the epitaxial structure A (a) and B (b). (Inset) measured breakdown characteristics, with BV _CEO reported at both 1 ka/cm² and 10 ka/cm².

The small-signal performances of the transistors were measured from 0.2 to 50 GHz. Figure 3 shows |h ₂₁|², U, MAG/MSG and the corresponding cut-off frequencies f _T/f _MAX for the epitaxial structures A and B at (a), (b) peak f _T bias point and (c), (d) peak f _MAX.

Figure 3.

RF characteristics of a (0.25 × 10) µm² DHBT. |h₂₁|², U and MAG/MSG are reported for (a) and (b) best f _T bias condition and (c) and (d) best f _MAX bias condition for the epitaxial structure A (a)–(c) and B (b)–(d).

The epitaxial structure A shows f _T = 0.48 THz at V _CE = 1.0 V, J _C = 10.3 mA/µm² and f _MAX = 1.13 THz at V _CE = 1.1 V, J _C = 12.4 mA/µm². The epitaxial structure B shows f _T = 0.51 THz at V _CE = 1.0 V, J _C = 9.4 mA/µm² and f _MAX = 1.16 THz at V _CE = 2.0 V, J _C = 11.7 mA/µm².

Both structures have excellent small-signal performances, but to better understand their dependence on the applied bias, it is useful to look at the evolution of the cutoff frequencies f _T/f _MAX over different biases. Figure 4 shows the I-V curves of a (0.25 × 10) µm² DHBT with f _T and f _MAX superposed on them for the epitaxial structure A (Fig. 4a and 4c) and B (Fig. 4b and 4d). It is clear how for the epitaxial structure B the range of high small-signal performance is extended both in I _C and V _CE with respect to the structure A. This feature is highly attractive for a PA design, as it gives great flexibility in the PA cell biasing. Having such high and stable cut-off frequencies enables to reach very high P _OUT and PAE without compromising on small-signal RF performances.

Figure 4.

Contours showing the variation of f _t (a)–(b) and f _max (c)–(d) with bias superposed over the I-V curves of a (0.25 × 10) µm² DHBT for the epitaxial structure A (a)–(c) and B (b)–(d). Each colour contour corresponds to a 2.5% reduction from peak f _t and f _max.

Large-signal load-pull measurements

In order to investigate the power performances of InP/GaAsSb DHBTs and to properly highlight the differences between the epitaxial structures A and B, the devices were characterized at Vertigo Technologies, by means of an active vector-modulation solution [Reference De Martino, Galatro, Romano, Parisi and Spirito6].

The bias choice is of paramount importance in large-signal measurements, as it affects dramatically figures of merit such as P _OUT, G _OP and PAE. Transistors used in PAs are usually biased in different conditions than those at which they reach their best small-signal performance. In order to achieve class-A operation, we used a collector current density of J _C = 8.0 mA/µm², around 70% of the density of current needed for peak f _MAX, and half of the value J _MAX for which there is the onset of thermal effects in the I-V curves. This value of J _C allows an active load line without the risk of current-clipping.

The transistors of both epitaxial structures were measured with the collector-emitter voltage starting from V _CE = 1.2 V and increased until degradation. For structure A, the degradation happened after V _CE = 1.8 V, whereas for B after V _CE = 2.0 V. From now on, we will only focus on the results for these bias points.

The load-pull measurements were done at four frequencies, 140, 150, 160 and 170 GHz. First, the optimal load for different input power P _IN was found. Figure 5 shows the measured P _OUT and PAE contours at 140 and 170 GHz for the epitaxial structure A (Fig. 5a and 5b) and B (Fig. 5c and 5d). For the structure A, the contours do not fully close at 140 GHz, but they do at 170 GHz. For both structures, P _OUT and PAE contours do not coincide, yet they show a good overlap. Loading a transistor close to the optimum load for both P _OUT and PAE is a desirable feature, because it allows a good compromise between output power and efficiency. It is also clear that the optimum load Z _L for both structures at both 140 GHz and 170 GHz is close to the centre of the Smith chart. This is an appealing feature when designing a power amplifier, because the output impedance of the transistor requires a low impedance transformation ratio to a 50 Ω system, a valuable quality in application requiring a low-loss broadband impedance match.

Figure 5.

Load-pull contours at P _IN,SAT for P _OUT (blue) and PAE (red) of a (0.25 × 10) µm² DHBT for the epitaxial structure A (a)–(b) and B (c)–(d) at V _CE = 1.8 V, J _C = 8.0 ma/µm² for a and V _CE = 2.0 V, J _C = 8.0 ma/µm² for B. The contours reflect measurements done at 140 ghz in (a) and (c) and 170 ghz in (b) and (d).

After performing the load-pull measurements, power sweeps were carried out with optimum load impedance Z _L,OPT to determine the highest P _OUT and PAE. Figure 6 reports the operational gain G _OP and PAE against the output power P _OUT between 140 and 170 GHz, in steps of 10 GHz, for the epitaxial structure A (a) and B (b), respectively, for a (0.25 × 10) µm² DHBT.

Figure 6.

Gain and PAE versus P _OUT at different frequencies of a (0.25 × 10) µm² DHBT for the epitaxial structure A (a) and B (b). The load is matched for maximum output power.

Figure 7.

Thermal resistance R _TH (a) and junction temperature T _J (b) for the epitaxial structures A (blue) and B (red) measured at V _CE = 1.1 V and J _C = 10 mA/µm².

The two structures exhibit quite different behaviours. By increasing the frequency, the transistor realized with the epitaxial structure A shows decreasing G _OP, PAE and P _OUT. Instead, the transistor realized with the structure B exhibits decreasing gain, but almost unchanged PAE and P _OUT. The results are summarized in Tables 3 and 4.

Table 3.

Measured gain at –1 dB compression, output power at –3 dB compression and PAE at different frequencies for the epitaxial structure A

Table 4.

Measured gain at –1 dB compression, output power at –3 dB compression and PAE at different frequencies for the epitaxial structure B

Epitaxial structure B shows a higher gain, due to the superior small-signal gain at the bias point for which the best large-signal performances are observed, as reported in Fig. 4c and 4d.

Both structures offer good saturated output power and very high efficiency. This demonstrates the excellent power performance of Type-II InP-DHBTs. To the best of the authors’ knowledge, these results represent a record in terms of PAE for the entire G-band.

Thermal characterization

In order to further characterize and understand the differences between the two epitaxial structures and thus, the effect that a thinner subcollector has on the performances of a InP-DHBT, the transistors were thermally characterized. It was reported [Reference Ciabattini, Arabhavi, Hamzeloui, Ebrahimi, Ostinelli and Bolognesi11–Reference Grandchamp, Nodjiadjim, Zaknoune, Koné, Hainaut, Godin, Riet, Zimmer and Maneux14] how engineering the emitter and collector epitaxial layers can offer significant advantages to the thermal resistance of a bipolar transistor.

In a DHBT, the majority of the heat is generated in the collector. The thermal conductivity of InP and GaInAs, if lattice matched to InP, is κ = 68 W/mK and κ = 5 W/mK, respectively. Thus, the removal of the 50 nm thick InP and the thinning of the GaInAs layer for the epitaxial structure B, is expected to bring great benefits to the transistor performance.

The thermal resistance R _TH is a metric of self-heating in a DHBT. When high, it indicates that the generated heat is not properly shunted, which then leads to an increased junction temperature T _J. An elevated T _J causes an earlier degradation of the device performances.

In any bipolar transistor a rise in T _J leads to a reduction of the base-emitter voltage V _BE required to achieve a given current density J _C. The thermal-electric feedback coefficient Φ takes this effect into account, and is defined as [Reference Liu, Chau and Beam15, Reference Müller, d’Alessandro, Falk, Weimer, Jin, Krattenmacher, Kuthe, Claus and Schröter16]:

(1)\begin{equation}\Phi {\left. { = - \frac{{\partial {V_{{\text{BE}}}}}}{{\partial T}}} \right|_{({I_C} = {\text{const}})}}\end{equation}

This coefficient is obtained from Gummel plots measured at different temperatures. Then, it can be used to calculate the thermal resistance R _TH of the device as:

(2)\begin{equation}{R_{{\text{TH}}}} = \,\frac{{{\Delta}{V_{\text{BE}}}}}{{{\Delta}{V_{{\text{CE}}}} \cdot {I_{\text{C}}} \cdot \Phi }}\end{equation}

where ΔV _BE is the voltage difference in the base-emitter voltage for a fixed collector current I _C when the collector-emitter voltage is changed by a fixed amount ΔV _CE. After R _TH is calculated, the junction temperature T _J can be derived by using:

(3)\begin{equation}\,\,\,\,\,\,{T_{\text{J}}} = {T_{\text{A}}} + {R_{{\text{TH}}}} \cdot {V_{{\text{CE}}}} \cdot {I_{\text{C}}}\end{equation}

where T _A is the ambient temperature. Figure 7 shows the results of the extracted thermal resistance and the calculated junction temperature of both epitaxial structures for different emitter lengths and for an emitter width W _E = 0.25 µm. The results are reported for V _CE = 1.1 V and J _C = 10 mA/µm².

The epitaxial structure B shows, for the emitter length L _E = 10 µm, an improvement of more than 10% in thermal resistance, compared with the structure A and a similar reduction in junction temperature. These results are in agreement with what was reported in [Reference Ciabattini, Arabhavi, Hamzeloui, Ebrahimi, Ostinelli and Bolognesi11].