Circuit analysis

The proposed three-way planar power divider is presented in Fig. 1. It features a main block (shown as BLOCK), which consists of three transmission lines (each with characteristic impedance Z ₁). All lines have an arbitrary electrical length θ (0° ≤ θ ≤ 90°) at the midpoint frequency of operation. The divider also employs two isolation resistors (each with value R) placed between ports 2 and 3 and between ports 3 and 4, respectively.

Figure 1.

The proposed three-way wideband planar power divider employing transmission lines of arbitrary length θ.

The extra transmission lines with characteristic impedances Z ₂ and Z ₃ and length θ at the input (port 1) and output (port 3), respectively, achieve the wideband characteristics of the proposed power divider. In this work, we set θ = 45° to achieve a compact design. If we increase θ το 90°, the bandwidth will be increased but not significantly. However, this increase in θ leads to an increase in the total length of the divider, as reported in [Reference Tsitsos, Anastassiu and Papatsoris15]. On the other hand, if we make θ < 45° to achieve a more compact design, the bandwidth will be decreased to some extent and the lines will become very short, leading to coupling effects and difficulties in implementation.

Equal power splitting is achieved by employing transmission lines with the same characteristic impedance Z ₁ inside the BLOCK (Fig. 1). The input and output lines with characteristic impedances Z ₂ and Z ₃, respectively, also achieve impedance matching. The derived equations for the input impedances Z _inC and Z′_inC (see Fig. 1) are set equal to Z ₀ and Z _in3, respectively, by imposing the matching condition at ports 2 and 3, as shown in equations (9) and (16).

The input impedances Z _in1 and Z _in3 are given as follows:

(1)\begin{equation}{Z_{\rm{in1}}} = {\ }{Z_2}{{{{\rm Z}_0} + j{Z_2}\tan {{\theta }}} \over {{Z_2} + j{Z_0}\,\tan {{\theta }}}},\end{equation}

(2)\begin{equation}{Z_{{\rm{in}}3}} = {Z_3}{{{Z_0} + j{Z_3}\,\tan \theta } \over {{Z_3} + j{Z_0}\,\tan \theta }}.\end{equation}

Considering the components contained in the BLOCK (see Fig. 1), we initially apply a voltage source to port 2. Assuming ideal isolation at the remaining output ports, the voltages at ports 3 and 4 must be zero (i.e., V ₃ = V ₄ = 0). Therefore, from the BLOCK shown in Fig. 1, the circuit shown in Fig. 2 can be derived.

Figure 2.

The circuit derived from the BLOCK (shown in Figure 1) by applying a voltage at port 2.

Based on Fig. 2, Z _inA can be calculated as follows:

\begin{equation*}{1 \over {{Z_{{\rm{in}}A}}}} = {1 \over {{Z_{{\rm{in}}1}}}} + {1 \over {j{Z_1}\,\tan \theta }} + {1 \over {j{Z_1}\,\tan \theta }},\end{equation*}

which results in the following equation:

(3)\begin{equation}{Z_{{\rm{in}}A}} = {{{Z_{{\rm{in}}1}} \cdot j{Z_1}\,\tan \theta } \over {j{Z_1}\,\tan \theta + 2{Z_{{\rm{in1}}}}}}.\end{equation}

In equation (3), by substituting Z _in1 from equation (1), the following equation can be obtained:

(4)\begin{equation}{Z_{{\rm{in}}A}} = {{j{Z_0}{Z_1}{Z_2}\,\tan \theta - {Z_{\rm{1}}}{Z_2}^2\,{\rm{ta}}{{\rm{n}}^{\rm{2}}}\theta } \over {j{Z_1}{Z_2}\,\tan \theta - {Z_{\rm{0}}}{Z_1}\,{{\tan }^2}\theta + 2{Z_0}{Z_2} + j2{Z_2}^2\,\tan \theta }}.\end{equation}

Also, based on Fig. 2, the input impedance Z _inB can be written as follows:

(5)\begin{equation}{Z_{{\rm{in}}B}} = {Z_1}{{{Z_{{\rm{in}}A}} + j{Z_1}\,\tan \theta } \over {{Z_1} + j{Z_{{\rm{in}}A}}\,\tan \theta }}.\end{equation}

In equation (5), by substituting Z _inA from equation (4), the following equation can be obtained:

(6)\begin{equation}{Z_{{\rm{in}}B}} = {{j{Z_{{\rm{in}}1}}{Z_1}\,\tan \theta - {Z_1}^2\,{{\tan }^2}\theta + j2{Z_1}{Z_{{\rm{in}}1}}\,\tan \theta } \over {j{Z_1}\,\tan \theta + 2{Z_{{\rm{in1}}}} - {Z_{{\rm{in}}1}}\,{{\tan }^2}\theta }}.\end{equation}

Furthermore, based on Fig. 2, the input impedance Z _inC can be written as follows:

(7)\begin{equation}{Z_{{\textrm{inC}}}} = {{R \cdot {Z_{{\textrm{in}}B}}} \over {R + {Z_{{\textrm{in}}B}}}}.\end{equation}

In equation (7), by substituting Z _inB from equation (6), the following equation can be obtained:

(8)\begin{equation}{Z_{inC}} = {{R\left[ {j3{Z_1}{Z_2}\tan \theta \cdot {{{Z_0} + j{Z_2}\tan {{\theta }}} \over {{{Z}_2} + j{Z_0}\tan {{\theta }}}} - {Z}_{\textrm{1}}^{\textrm{2}}\ {{\tan }^2}\theta } \right]{\ }} \over {\begin{array}{c} R\left[ {j{Z_1}\tan {{\theta }} + {{\text{Z}}_{\textrm{2}}}{{{Z_0} + j{Z_2}\tan \theta } \over {{{\textrm Z}_2} + j{Z_0}\tan {{\theta }}}} \cdot (2 - {{\tan }^2}{{\theta )}}} \right] \\ + \left[ {j3{Z_1}{Z_2}\tan {{\theta }}{{{Z_0} + j{Z_2}\tan {{\theta }}} \over {{Z_2} + j{Z_0}\tan {{\theta }}}} - {Z}_1^2{\ {\tan }^2}\theta } \right]\end{array}}}.\end{equation}

The above equation can also be derived if a voltage source is applied to port 4 because the divider of Fig. 1 is symmetric along its central axis.

The matching condition at port 2 requires

(9)\begin{equation}{Z_{{\textrm{in}}C}} = {Z_0}.\end{equation}

Next, we apply a voltage source to port 3. Assuming ideal isolation at the remaining output ports, the voltages at ports 2 and 4 must be zero (i.e., V ₂ = V ₄ = 0). Therefore, from the BLOCK shown in Fig. 1, the circuit shown in Fig. 3 can be derived.

Figure 3.

Circuit derived from the BLOCK (shown in Figure 1) when applying a voltage at port 3.

Based on Fig. 3, Z′ _inA can be calculated as follows:

\begin{equation*}{1 \over {{{Z'}_{{\rm{in}}A}}}} = {1 \over {{Z_{{\rm{in}}1}}}} + {1 \over {j{Z_1}\,\tan \theta }} + {1 \over {j{Z_1}\,\tan \theta }},\end{equation*}

which results in the following equation:

(10)\begin{equation}{{{Z'}_{{\rm{in}}A}}} = {{{{\rm Z}_{in1}} \cdot j{Z_1}\tan {{\theta }}} \over {j{Z_1}\,\tan {{\theta }} + {\rm{2}}{{{{Z}}}_{{\rm{in1}}}}}}\end{equation}

In equation (10), by substituting Z _in1 from equation (1), the following equation can be obtained:

(11)\begin{equation}{Z'_{{\rm{in}}A}} = {{j{Z_1}{Z_2}\,\tan \theta \cdot \left( {{Z_0} + j{Z_2}\,\tan \theta } \right)} \over {j{Z_1}\,\tan \theta \cdot \left( {{Z_2} + j{Z_0}\,\tan \theta } \right) + 2{Z_2} \cdot \left( {{Z_0} + j{Z_2}\,\tan \theta } \right)}}.\end{equation}

Also, based on Fig. 3, the input impedance Z′ _inB can be written as follows:

(12)\begin{equation}{Z'_{{\rm{in}}B}} = {Z_1}{{{{Z'}_{{\rm{in}}A}} + j{Z_1}\,\tan \theta } \over {{Z_1} + j{{Z'}_{{\rm{in}}A}}\,\tan \theta }}.\end{equation}

In equation (12), by substituting Z′ _inA from equation (10), the following equation can be obtained:

(13)\begin{equation}{Z'_{{\rm{in}}B}} = {Z_1}{{{\begin{array}{c} - 3{Z_1}{Z_2}^2\,{{\tan }^2}\ \theta - {Z_1}^2{Z_2}\,{{\tan }^2}\ \theta + j{Z_0}{Z_1}{Z_2}\,\tan \theta \\ - j{Z_0}{Z_1}^2\,{{\tan }^3}\ \theta + j2{Z_0}{Z_1}{Z_2}\,\tan \theta \end{array}}} \over {{\begin{array}{c} - {Z_0}{Z_1}^2\,{{\tan }^2}\ \theta + 2{Z_0}{Z_1}{Z_2} - {Z_0}{Z_1}{Z_2}\,{{\tan }^2}\ \theta \\ + j{Z_1}^2{Z_2}\,\tan \theta + j2{Z_1}{Z_2}^2\,\tan \theta - j{Z_1}{Z_2}^2\,{{\tan }^3}\ \theta \end{array}}}}.\end{equation}

Furthermore, based on Fig. 3, the input impedance Z′ _inC can be written as follows:

(14)\begin{equation}{Z'_{{\textrm{in}}C}} = {{R{{Z'}_{{\textrm{in}}B}}} \over {R + 2{{Z'}_{{\textrm{in}}B}}}}.\end{equation}

In equation (14), by substituting Z′ _inB from equation (12), the following equation can be obtained:

(15)\begin{align} {{Z{^{\prime}}}_{{\rm{in}}C}} & = {{\begin{array}{c}R{Z_1}\left( - 3{Z_1}{Z_2}^2\,{{\tan }^2}\ \theta - {Z_1}^2{Z_2}\,{{\tan }^2}\ \theta + j{Z_0}{Z_1}{Z_2}\,\tan \theta \right.\\ \left. - j{Z_0}{Z_1}^2\,{{\tan }^3}\ \theta + j2{Z_0}{Z_1}{Z_2}\,\tan \theta \right)\end{array}} \over {\begin{array}{c} R\left( - {Z_0}{Z_1}^2\,{{\tan }^2}\ \theta + 2{Z_0}{Z_1}{Z_2} - {Z_0}{Z_1}{Z_2}\,{{\tan }^2}\ \theta \right.\\ \left.+ j{Z_1}^2{Z_2}\,\tan \theta + j2{Z_1}{Z_2}^2\,\tan \theta - j{Z_1}{Z_2}^2\,{{\tan }^3}\ \theta \right)\end{array}}} \\ &\qquad+ 2{Z_1}\left( - 3{Z_1}{Z_2}^2\,{{\tan }^2}\ \theta - {Z_1}^2{Z_2}\,{{\tan }^2}\ \theta + j{Z_0}{Z_1}{Z_2}\,\tan \theta \right.\\ &\qquad\quad\left.- j{Z_0}{Z_1}^2\,{{\tan }^3}\ \theta + j2{Z_0}{Z_1}{Z_2}\,\tan \theta \right). \end{align}

The matching condition at port 2 requires

(16)\begin{equation}{Z'_{{\textrm{in}}C}} = {Z_{{\textrm{in}}3}}.\end{equation}

Implementation, results, and discussion

Equations (8), (9) and (15), (16) can be used as the design equations of the proposed power divider. These equations are satisfied for a number of solutions. Thus, the variety of parameter values provides design flexibility. To achieve a compact design, θ = 45° was selected at a midpoint frequency of 3 GHz. Also, by selecting Z ₀ = 50 Ohm, R = 100 Ohm, and Z ₁ = 90 Ohm, equations (8), (9) and (15), (16) yield practically realizable impedance values (Z ₂ = 23.23 Ohm and Z ₃ = 47.91 Ohm). These parameter values are summarized in Table 1.

Table 1.

Electrical parameter values for the proposed power divider in Figure 1

The proposed three-way wideband planar power divider shown in Fig. 1 was fabricated on a printed circuit board (PCB) using a TACONIC substrate with a typical dielectric constant of 2.2 (Fig. 4). The layout of the proposed power divider was produced using the Advanced Design System simulation software. Then, we placed a mask of the layout on the top copper surface of the TACONIC substrate and immersed it into a solution of sodium hydroxide to remove the unwanted copper. Thus, the upper conductors of the microstrip lines with the desired dimensions were fabricated. Commercial 100-Ohm resistors were used to achieve the necessary isolation between the output ports. These resistors could, in principle, cause some parasitic effects. However, in the operating frequency range of the divider, these effects are negligible. We employed an Agilent E5071C vector network analyzer to measure the scattering parameters (amplitude and phase) of the fabricated PCB over the frequency range 1–5 GHz. Before conducting measurements, we performed the standard transmission–line–through calibration procedure. The graphs in Fig. 5 show the simulated and experimental responses of the proposed divider. Good agreement can be observed. The discrepancies are mainly due to the limited accuracy of the etching process and the effect of the connectors, which were not included in the simulation. Due to our limited lab resources, we could not perform any calibration or correction procedures to address the discrepancies caused by the etching process and connectors during the measurement process. It is evident that in the frequency range 1.6–3.3 GHz (a fractional bandwidth of ${{3.3 - 1.6} \over {2.45}} \cong $ 69.4%), the proposed divider achieves equal power split (∼32%, −4.9 ± 0.4 dB insertion loss) between the input and each output port and good matching and isolation characteristics. The measured return loss is better than −10 dB at all ports, and the measured maximum isolation is close to −30 dB. The maximum measured amplitude imbalance is ∼0.8 dB. The maximum measured phase imbalance between ports 2 and 4 is ∼8 degrees, whereas that between ports 2 and 3 (or 4 and 3) is ∼51 degrees. This is due to the extra length θ of the line with characteristic impedance Z ₃ shown in Fig. 1.

Figure 4.

Fabricated PCB of the proposed power divider.

Figure 5.

Measured results for (a) input return loss, (b) output return loss, (c) insertion loss, (d) port isolation, (e) amplitude imbalance, and (f) phase imbalance of the proposed three-way planar divider shown in Figure 1

Generally, the phase imbalances measured are not significant in applications requiring an accurate splitting ratio. However, the phase imbalances measured between certain ports, although acceptable, may have an impact in phase array applications. In cases requiring very small phase imbalances, an appropriate phase shifter could be used.

A performance comparison of the proposed planar power divider with the performance of previously published designs is shown in Table 2. It is evident that the performance of the proposed design is better than the performance of most other designs in terms of insertion loss, isolation, bandwidth, and size but falls short in terms of return loss. However, its design flexibility, easy implementation, and expansion to an n-way structure make it an attractive proposition.

Table 2.

Performance comparison of the proposed structure with the performance of previously published works