Introduction
Frequency multiplication can be achieved using microwave diodes, as varactors [Reference Vu, Takano and Fujishima1] and Schottky ones ([Reference He, Wang, Liu, Cao, Kuai and Yu2] and [Reference Wu, Jin, Zhou, Wei, Liu and Lin3]), however, with conversion losses. On the other hand, the use of transistors in non-linear regime can provide both frequency multiplication and conversion gain [Reference Bera4].
Balanced circuit topologies are often used in active microwave circuits due to the advantages in performance they present, e.g. enhancing the RF output power (Pout) and matching of an amplifier. In active frequency multiplier design, transistor-based balanced frequency doublers (BFDs) exhibit both higher fundamental signal suppression, crucial to attenuate this powerful signal, and higher Pout in comparison to the single-ended (SE) architecture.
Recent works that present active frequency doublers (FD) using different transistor technologies and working at different frequency bands have been studied. Some active doublers working at MW and millimeter wave bands found in the literature use Si CMOS [Reference Hao, Tang, Ding, Du, Du, Tang, Gu and Chang5], InP HBT [Reference Nguyen, Shepard, Wagner, Stameroff and Pham6] or Si RFSOI ADNFET [Reference Abbasi, Thapliyal, Mohammad Ashab Uddin and Lee7] transistors, among others. In the case of [Reference Hao, Tang, Ding, Du, Du, Tang, Gu and Chang5], nonlinear transmission lines are used to generate the second harmonic, and a distributed power amplifier (PA) is added to obtain conversion gain. Regarding [Reference Nguyen, Shepard, Wagner, Stameroff and Pham6], the novelty of the presented FD resides in the Marchand balun used at its input, that present low losses and low imbalances, required for a high fundamental signal suppression. A push-push doubler is proposed in [Reference Abbasi, Thapliyal, Mohammad Ashab Uddin and Lee7], that adds a differential PA at its output. Some common features of these circuits are the use of PAs and the wide bandwidth they present. Another push-push FD working at lower frequencies (input 
$f_0 = 15\,\mathrm{GHz}$) is presented in [Reference Vissers, Zirath and Lasser8], where GaN/SiC HEMTs are used. It also uses a Marchand balun and, in this case, conversion gain is achieved without the use of an amplifier.
Regarding hybrid SE FDs working at closer frequencies to that used in this work, we found [Reference Srivastava, Gaddam, Dhar and Narasimha Rao9] and [Reference Yuk, Branner and Wong10]. The doubler in [Reference Srivastava, Gaddam, Dhar and Narasimha Rao9] (
$f_0 = 4.65 - 4.95\,\mathrm{GHz}$) includes a low-pass filter (LPF) at the input, to select the fundamental signal, and a band-pass filter (BPF) at the output, to reject the fundamental and harmonics signals above the 2nd. It presents losses in the operating bandwidth, however, the fundamental rejection is around 47 dBc. In [Reference Yuk, Branner and Wong10] two doublers are presented. One using a SiC MESFET working at input 
$f_0 = 2\,\mathrm{GHz}$ and another using a GaN HEMT at 
$f_0 = 3.33\,\mathrm{GHz}$. Although the transistors are different, the design procedure is similar. No bias networks are included in the design and in addition to the input and output matching networks, reflector stubs at 
$2f_0$ at the input, and at f 0 at the output, are presented.
Most of the published research works on the design of high frequency BFDs are related to GaAs-based MMIC technology. Regarding broadband BFDs using this semiconductor, in [Reference Lee, Chao, Tsai, Huang, Lien, Tsai and Huei11] (input 
$f_0 = 6-11\,\mathrm{GHz}$) and [Reference Nguyen, Nguyen, Fujii and Pham12] (input 
$f_0 = 3-23\,\mathrm{GHz}$), power amplifier stages are required to obtain conversion gain, while in [Reference Deng and Wang13] (input 
$f_0 = 15-25\,\mathrm{GHz}$) the conversion gain is negative, with losses around 5-7 dB. The same happens in [Reference Kaho, Yamaguchi, Okazaki and Uehara14] (input 
$f_0 = 4.4\,\mathrm{GHz}$), where the BFDs conversion losses are around 4 dB. Regarding the input couplers used in these works, a variety of options are presented. In [Reference Lee, Chao, Tsai, Huang, Lien, Tsai and Huei11] and [Reference Deng and Wang13] reduced size rat-race couplers are designed, using in the first case 
$\frac{\lambda}{8}$ lines and MIM capacitors, and inductors and MIM capacitors in the second case. In [Reference Nguyen, Nguyen, Fujii and Pham12] a Marchand balun is used and in [Reference Kaho, Yamaguchi, Okazaki and Uehara14] an active balun.
In the framework of GaN technology, which exhibits higher output power levels and efficiency, two BFDs were found using GaN HEMTs. In [Reference Sonnenberg, Verploegh, Pinto and Popović15], one SE FD, one BFD, and a frequency tripler are presented in MMIC technology. In particular, the BFD operates at an input f 0 from 45 to 50 GHz and presents a maximum 2nd harmonic conversion gain (
$G_{c2f_{0}}$) of 3.8 dB and fundamental signal suppression greater than 55 dBc. In [Reference Ma and Bi16], the BFD is used in series with a balanced frequency tripler to build a MMIC sixtupler.
A comparison only of the mentioned doublers at frequencies close to this work is shown in Table 1.
Comparison of the state-of-the-art FDs working in similar frequency bands.
* Data including the Pas.
In this work, a hybrid BFD circuit using packaged GaN HEMTs and working at 
$2f_0 = 4.9\,\mathrm{GHz}$ with no amplification stage, is designed and its performance validated with measurements. This paper extends the BFD research presented on a previous conference paper by the authors [Reference Morales-Fernandez, Marante-Boado, Toimil-Cornado, Fernandez-Barciela, Martin-Rodriguez and Tasker17], in which other FDs were also designed and discussed. In Section 2, the detailed design methodology of the SE FDs that integrate the balanced structure is included, as well as its performance evaluation through the design and measurements of a prototype. Next, in Section 3, the procedure to design the BFD is described, in particular, the design of the input coupler, that presents a compact structure not applied before in this type of circuits. In Section 4, the measured performance of the designed BFD prototype is evaluated and compared with the predictions in simulation. Finally, Section 5 shows a comparison between the SE FD and the BFD, that shows the output power and fundamental signal rejection improvements using the balanced topology.
Single-ended frequency doubler
Initially, a SE FD working at 
$2f_0 = 4.9\,\mathrm{GHz}$ was designed, in order to use it in the balanced structure. The Qorvo GaN TGF2977-SM transistor was selected due to its bandwidth, gain and power performance. The model provided by Modelithics was used in the ADS simulations.
The first step is to choose the most adequate bias point for this HEMT, enhancing even harmonics generation under nonlinear behavior. Since our goal is to maximize the 2nd harmonic signal in an efficient manner, fundamental signal needs to be suppressed. In the literature, a class B bias point is suggested for FD design. Therefore, a study to find the best bias point was carried out using both simulations and measurements. Several DC gate voltage (VGS) values around class B and input powers (Pin) were swept to find the conditions providing the maximum 
$G_{c2f_{0}}$. This conversion gain is the figure of merit optimized in this step, since it will impact both the circuit power added efficiency (PAE) and self-heating, while the power delivered by the GaN HEMT will be doubled using the balanced topology. A higher 
$G_{c2f_{0}}$ with enough RF power will avoid the need for a booster amplifier. For these simulations, fundamental load was short-circuited, the perfect load to reject the fundamental signal. In Fig. 1, the 
$G_{c2f_0}$ contours show that the maximum is achieved at VGS=-3 V and 
$P_{in} = 10\,\mathrm{dBm}$. In addition, in Fig. 2, the 
$G_{c4f_0}$ contours in the same conditions are shown. We can conclude that, in simulation, 
$V_{GS} = -3.2\,\mathrm{V}$ seems an adequate bias point to design the FD, since a high 
$G_{c2f_{0}}$ is obtained, as well as low 
$G_{c4f_0}$ and high Pin, allowing in this case higher 2nd harmonic output power (
$P_{out2f_0}$). A similar study was performed with measurements using an VSA (Vector Signal Analyzer), providing equivalent results.
$G_{c2f_0}$ simulated contours sweeping both Pin and VGS.
$G_{c4f_0}$ simulated contours sweeping both Pin and VGS.
To design the bias networks (shown in Fig. 8), decoupling capacitors were used to block the DC, and 
$\frac{\lambda}{4}$ lines with a radial stub (which acts as a short circuit at 2.45 GHz at the input and at 4.9 GHz at the output) to minimize RF losses. In addition, several parallel RC branches are added to filter out low-frequency spurious signals and enhance out-of-band stability. A series resistor in the input is added to further improve stability.
The next step is to find in simulation the second harmonic output impedance (
$Z_{L2f_0}$) that provides, at the chosen Pin, the maximum 
$G_{c2f_0}$ by using 2nd harmonic load-pull (LP), shown in Fig. 3. This impedance, 
$Z_{L2f_0} = 50(0.209 + 0.562j) = 10.45 + 28.1j$, is the one used to design the output matching network (OMN), shown in Fig. 4. Then, accessing to the transistor intrinsic nodes, available in the Modelithics model, the intrinsic 2nd harmonic FET impedance (
$Z_{L2f_0}^{int}$) is computed. This step is crucial since that will be the target impedance in the doubler design. The OMN network includes a single transmission line (TL) resonator to force a high reflective load in 
$Z_{Lf_0}$ at transistor’s drain. We decided to also add another one for 
$Z_{L4f_0}$, since the 
$4f_0$ signal becomes stronger when Pin increases, as shown in Fig. 2. No additional suppression is added for the 3rd harmonic, since at the chosen bias point it is relatively small compared to the even harmonics. For matching the 
$Z_{L2f_0}$, two 
$\frac{\lambda}{4}$ TLs, each line with different characteristic impedance, have been added after the drain bias network. That is why part of the drain bias network is also included in Fig. 4. In Fig. 5 it can be seen that this OMN presents 0.65 dB of losses at the 2nd harmonic. The effect of the 
$\frac{\lambda}{4}$ stubs at f 0 and 
$4f_0$ can also be seen in the high losses, as well as in the high reflective impedances achieved at these frequencies. Moreover, it is noticeable that there is no need to tune 
$Z_{L3f_0}$ since the 3rd harmonic is highly suppressed.
$G_{c2f_0}$ simulated contours obtained at Pin=10 dBm with second harmonic LP, showing the impedance that maximizes 
$G_{c2f_0}$.
Output matching network design. Part of the drain bias network and decoupling capacitor are shown in the box.
Simulated output matching network (a) S 11 and S 21 magnitude in dB. (b) S 11 magnitude and phase.
At the input, conjugate matching at f 0 is used and a short-circuit for 
$Z_{S2f_0}$ using a single resonator is added, in order to reflect the 2nd harmonic signal towards the FET input. The extrinsic source impedance is 
$Z_{Sf_0} = 21 + 20\mathrm{j}\,\Omega$, achieved using a single 20 Ω TL. This network presents the performance shown in Fig. 6, where we can highlight its low losses, that contribute to maintain the 
$G_{c2f_0}$ values.
Input matching network simulated S 11 and S 21 parameters.
Simulation results vs input power for the FD circuit are shown in Fig. 7, where the conversion gains for the fundamental and harmonics up to the 4th are shown. The maximum predicted 
$G_{c2f_0}$ is 12.3 dB, and the harmonic suppression is around 30 dBc for the fundamental and larger for the undesired higher harmonics.
SE FD simulated conversion gains up to the 4th harmonic.
Single-ended prototype
The microstrip FD prototype PCB (RO4003C substrate) was processed by laser milling. The circuit was assembled and attached to a copper heat sink. In Fig. 8 the hybrid SE FD prototype is shown.
Photo of the designed SE 4.9 GHz FD prototype.
Small-signal measurements
Using a VNA P9377B, broadband S-parameter measurements were performed. In Fig. 9, the measured S 11 is shown in comparison to the simulated one. At the fundamental frequency, S 11 is below −12.5 dB, hence good matching was obtained at the input, including good suppression of the 2nd harmonic.
Measured (blue dashed line) and simulated (red continuous line) SE FD prototype S 11.
Large-signal measurements
Figure 10 shows the set-up used in this work to perform large-signal measurements. A DC source is used for biasing the HEMT at 
$V_{DS} = 32\,\mathrm{V}$ and DC drain current (
$I_{DS}) = 0.5\,\mathrm{mA}$. Moreover, a booster amplifier was placed after the E8257D signal generator to provide the desired Pin. The receiver (VSA CXA N9000A) bandwidth was capable of measuring above the 4th harmonic, and this instrument was protected using an attenuator. Figure 11 shows the FD prototype power sweep measurements in comparison with simulations. Fundamental signal suppression is around 20 dBc in measurements, while reaching 30 dBc in simulation. Regarding 3rd and 4th harmonics, measured suppression is close to 50 dBc or higher. Measured maximum 
$G_{c2f_0}$ was 12.2 dB, similar to the simulated one.
Measurement set-up used to perform large signal measurements.
Measured (dashed line) and simulated (continuous line) single-ended FD prototype conversion gains up to the 4th harmonic.
Balanced frequency doubler design
Figure 12 shows the designed BFD block diagram. As indicated before, with this configuration we should expect higher f 0 signal rejection and increased 
$P_{out2f_0}$ over the single-ended case. For this purpose, the SE FD designed in the previous section was used as the two FD1. At the input, a 180∘ hybrid coupler is required to split and phase-shift the input signal. At the output, a combiner must be used to add in phase both output signals delivered by the SE FDs.
Balanced FD block diagram from [Reference Morales-Fernandez, Marante-Boado, Toimil-Cornado, Fernandez-Barciela, Martin-Rodriguez and Tasker17].
Input 180∘ hybrid coupler design
A rat-race hybrid coupler is a conventional passive structure used to split a signal into two with a 180∘ shift. However, its area can be significantly large at low microwave frequencies, such as 2.45 GHz, due to the use of 
$\frac{\lambda}{4}$ and 
$3\frac{\lambda}{4}$ sections and conventional substrates. Thus, its miniaturization using space-filling curves, as proposed in [Reference Ghali and Moselhy18] and [Reference Ghali and Moselhy19], was applied in this work to aid in circuit compactness. In particular, we used Moore curves at its first iteration, since increasing the iteration implies increasing the number of segments and hence, line coupling could happen. In our design, this curve contains 16 segments of 7 mm length each, computed using equation 1 from [Reference Ghali and Moselhy19]:
\begin{equation}
a_n = \frac{\pi R}{2 (4)^n},
\end{equation}where R is the standard rat-race radius and n is the iteration. Once designed, the obtained total area in this work was 390 mm 2, much reduced in comparison to the equivalent standard rat-race area, 994 mm 2. The difference in size can be appreciated in Fig. 13.
Left side: rat-race ring coupler at 2.45 GHz. Right side: equivalent coupler using Moore space-filling curves (from [Reference Morales-Fernandez, Marante-Boado, Toimil-Cornado, Fernandez-Barciela, Martin-Rodriguez and Tasker17]).
Single-ended FDs output combiner
A Wilkinson hybrid coupler was used to combine the Pout of both SE FDs. This coupler was designed at 
$2f_0$, hence was compact enough. Since several TLs were required after the input coupler to aid separating both SE FDs, bent microstrip transmission lines were also placed at the input of the Wilkinson coupler, providing the proper phase-shift correction for f 0 and the 2nd harmonic in a small space.
Balanced frequency doubler simulations
In Fig. 14, simulated conversion gains for the BFD are presented. It is shown that, although the maximum 
$G_{c2f_0}$ is 1 dB below the simulated SE FD, the Pin at this point is 4 dB higher, hence Pout has increased in 3 dB. Moreover, the f 0 suppression has improved around 10 dB, achieving almost 40 dBc for f 0 and harmonics up to the 4th.
BFD simulated conversion gains up to the 4th harmonic.
Balanced frequency doubler experimental results
A photo of the BFD prototype is shown in Fig. 15. It can be seen that both SE circuits are not completely symmetrical. TLs were added at the input of one of the circuits and at the output of the other one, to make feasible the connection to the input and output couplers, respectively. In addition, those TLs lengths are chosen in order to maintain the harmonics phase relationship needed to take advantage of the balanced structure. This relationship is shown in Fig. 12. Similar manufacture and test procedures as with the SE FD prototype were applied to the BFD. The small and large-signal set-ups were the same but including an extra DC power supply to bias both HEMTs. All results in this section are for an input 
$f_0 = 2.45\,\mathrm{GHz}$.
This work BFD prototype working at 
$2f_0 = 4.9\,\mathrm{GHz}$.
Measurements at different bias points
Several transistor bias points close to the one used in simulation were tested, in order to analyze which of them provided improved performance, to account for slight inaccuracies in the HEMT model, not optimized for sharp class B. Figure 16 shows a comparison of the BFD conversion gain when IDS is 0.2, 0.5 and 1 mA. It can be seen that the obtained maximum measured 
$G_{c2f_0}$ is 11.5 dB, achieving also good fundamental and other undesired harmonics suppression. Moreover, when 
$I_{DS} = 0.2\,\mathrm{mA}$, the maximum 
$G_{c2f_0}$ is achieved at higher Pin, which implies higher 
$P_{out2f_0}$. Therefore, next measurement tests are performed at this specific bias point.
Measured BFD conversion gains, up to the 3rd harmonic, at different bias points: 
$I_{DS} = 0.2\,\mathrm{mA}$ (blue), 0.5 mA (red) and 1 mA (magenta).
Small-signal measurements
In Fig. 17, S 11 is shown from 1 to 6 GHz. It can be seen that the bandwidth has increased significantly in comparison to the SE FD, due to the input coupler design, that presents more than 1.5 GHz of bandwidth, measured at a return loss of 10 dB. At f 0, S 11 is around -20 dB, which provides a good input match.
Measured (blue) and simulated (red) BFD prototype S 11.
Large-signal measurements
In Figs. 18 and 19, measured conversion gains and Pout up to the 3rd harmonic, respectively, vs Pin are shown. Fourth harmonic not shown for clarity, its measured suppression level higher than the 3rd one. The maximum measured 
$G_{c2f_0}$ is 11.5 dBm and it is achieved at 
$P_{in} = 14.8\,\mathrm{dBm}$. At this power, Pout is 26.3 dBm. Moreover, f 0 and 
$3f_0$ suppression exceeds 40 dBc in all the measured range, which is one of the main advantages using the balanced topology.
BFD prototype conversion gains simulated (continuous line) and measured (dashed line) vs Pin.
BFD prototype Pout from simulations (continuous line) and measurements (dashed line) vs Pin.
Next, in Fig. 20, measurements of 
$G_{f_0}$ and 
$G_{c2f_0}$ vs f 0 are compared with the results in simulation. If we consider the region in which the 
$G_{c2f_0}$ is above 5 dB, we obtain a bandwidth for input frequencies from 2.3 to 2.7 GHz, which means 400 MHz. This is equivalent to a 16% fractional bandwidth, hence in the onset of wideband. Moreover, although in simulation the maximum 
$G_{c2f_0}$ is found at a slightly higher frequency, the prototype achieves its best performance at 
$2f_0 = 4.9\,\mathrm{GHz}$.
BFD simulated (continuous line) and measured (dots) fundamental gain (red) and 2nd harmonic conversion gain (blue) at the Pin for maximum 
$G_{c2f_0}$ vs f 0.
To our knowledge, this is the first published BFD designed and validated experimentally in hybrid technology using packaged GaN HEMTs.
Comparison of the single-ended and balanced frequency doublers
In this section, the measured figures of merit of the SE FD and BFD are compared in order to show the enhancement in the performance using the balanced configuration. It should be noted that the SE FD measurements were performed at a bias point of 
$I_{DS} = 0.5\,\mathrm{mA}$, while in the BFD, 
$I_{DS} =\,0.2\,\mathrm{mA}$ was the bias DC current, determined after the study of different bias points with the BFD prototype, shown in the previous section.
In Fig. 21 it can be observed that the maximum 
$G_{c2f_0}$ is similar in both designs. However, it should be noted that it is achieved at a higher Pin in the BFD, due to the input hybrid coupler, since it implies the need of a Pin at least 3 dB higher than in the equivalent SE FD, and due to the differences in the bias points between both prototypes. Moreover, the f 0 signal rejection is approximately 20 dB higher in the BFD, as expected. Regarding the Pout, shown in Fig. 22, the reached 
$P_{out2f_0}$ at the point of maximum 
$G_{c2f_0}$ is higher at the BFD, since the RF power of the two implied transistors is added.
Comparison of the measured conversion gains between the SE FD (blue) and the BFD (red) of this work.
(a) Comparison of the measured 
$P_{out2f_0}$ between the SE FD (blue) and the BFD (red) of this work. (b) Comparison of the measured Pout at other harmonics between the SE FD (blue) and the BFD (red) of this work.
Conclusion
In this paper a balanced frequency doubler working at 
$2f_0 = 4.9\,\mathrm{GHz}$ using GaN packaged HEMTs is designed in hybrid technology and validated with measurements. From a careful selection of the HEMTs bias point, the validation of a preliminary single-ended design and the design of a Moore-space-filling curves-based 180∘ hybrid input coupler for compactness, a good RF performance was obtained both in simulations and in measurements of the fabricated prototype. No amplification stage was required, thanks to the performance capabilities of the GaN technology and the adequate selection of matching networks. A maximum measured conversion gain of 11.5 dB with a second harmonic output power of 26.3 dBm was obtained, while fundamental, 3rd and higher harmonics suppression exceeded 40 dBc.
Acknowledgements
The authors would like to thank the Spanish Ministerio de Ciencia, Innovación y Universidades (MCINU/AEI/10.13039/501100011033) under grants PID2020-116569RB-C33 and PID2023-147653OB-C33, the last one also funded by “ERDF A way of making Europe”, and Universidade de Vigo under Reasearch Staff Mobility grant. Moreover, our thanks to Modelithics and Qorvo for providing passive and active components models for simulation (under the University License Program) and to Cantabria University, Spain, for PCBs processing.
Competing interests
The authors report no conflict of interest.
Ainhoa Morales-Fernandez received the B.S. and M.S. degrees in telecommunication engineering from the Universidade de Vigo (University of Vigo, UVigo), Spain, in 2021, where she is currently pursuing the Ph.D. degree in communications engineering, specializing in electronics for communications. In 2018, she was an Intern with the atlanTTic Research Center for Telecommunication Technologies, Vigo, where she received advanced formation in hybrid power amplifiers and frequency doublers’ design in microstrip technology. Since 2020, she has been a Research Assistant at the AtlanTTic Research Center. Her research interests include nonlinear device modeling and microwave circuit design.
Monica Fernandez-Barciela received the M.Sc. degree in physics (electronics) from the University of Santiago de Compostela (USC), Spain, in 1989, and the Ph.D. degree in communications engineering from the University of Vigo (UVigo), Spain, in 1996. Her thesis research work was partly performed at the Fraunhofer-Institut (IAF), Germany, through different stay grants. She joined the UVigo Communications Technologies Department, in 1990, first as a FPI granted Ph.D. student, later as an Assistant Professor (1991) and an Associate Professor (1997) at the Vigo School of Communication Engineering. From July 2010 to September 2014, she was the Vice-Director of the Signal Theory and Communications Department, UVigo. From December 2017 to December 2019, she was the President of the IEEE Spanish Joint Chapter AP003/MTT017. Her main research work has been related to active device nonlinear black-box modeling, device characterization, and circuit design for communications applications.
Fernando Martin-Rodriguez received the Communications Eng. degree in 1993 and the Ph.D. degree in 1999, both from University of Vigo (Vigo, Spain). Joined University of Vigo as Assistant Prof. in 1995 (formerly, lecturer at University of La Coruña, Computer Science School). Nowadays, is Associate Prof. at Vigo’s Communications Eng. School (Vigo, Spain). Recipient of a fellowship to research at NIST (Gaythersburg, MD, USA) in 1997. His main research work has been done in image analysis and computer vision, data and wireless networks. He also have contributions in microwave electronics. He has published research papers in journals and conferences, and leaded contracts and research projects. He is the Member of the Spanish and Galician association of Communication Eng. Institution who awarded him with the “Better ITC project with social consciousness” prize in 2018.
Paul J. Tasker led a research position with Cornell, WI, USA, from 1983 to 1990, establishing HFETs as the technology of choice for high frequency applications. His collaboration with general electric led to the first use of HFET technology in radio telescopes used by NRAO to receive transmissions from NASA’s Voyager 2. From 1990 to 1995, he directed the GaAs monolithic microwave integrated circuit (MMIC) technology development with the Fraunhofer Institute (IAF), Freiburg, Germany, delivering state-of-the-art 60-100 GHz GaAs MMICs. In 1995, joined Cardiff University (U.K.), establishing the Centre for High-Frequency Engineering (CHFE), in 1996. The CHFE is now recognized internationally for its pioneering work in developing waveform engineering concepts and their application to microwave and millimeter-wave power amplifier (PA) design. He has more than 30 years of experience in design, fabrication, characterization, and modeling of high frequency devices. He is involved in collaborative projects with a wide range of academic and industrial partners. He was a Distinguished Microwave Lecturer with the IEEE MTT Society from 2008 to 2010.
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