Combinational logic circuits implement logical functions on a set of inputs. Used for control, arithmetic, and data steering, combinational circuits are the heart of digital systems. Sequential logic circuits (see Chapter 14) use combinational circuits to generate their next state functions.

In this chapter we introduce combinational logic circuits and describe a procedure to design these circuits given a specification. At one time, before the mid 1980s, such manual synthesis of combinational circuits was a major part of digital design practice. Today, however, designers write the specification of logic circuits in a hardware description language (like VHDL) and the synthesis is performed automatically by a computer-aided design (CAD) program.

We describe the manual synthesis process here because every digital designer should understand how to generate a logic circuit from a specification. Understanding this process allows the designer to better use the CAD tools that perform this function in practice, and, on rare occasions, to generate critical pieces of logic manually.

Asynchronous sequential circuits have state that is not synchronized with a clock. Like the synchronous sequential circuits we have studied up to this point, they are realized by adding state feedback to combinational logic that implements a next-state function. Unlike synchronous circuits, the state variables of an asynchronous sequential circuit may change at any point in time. This asynchronous state update – from next state to current state – complicates the design process. We must be concerned with hazards in the next-state function, since a momentary glitch may result in an incorrect final state. We must also be concerned with races between state variables on transitions between states whose encodings differ in more than one variable.

In this chapter we look at the fundamentals of asynchronous sequential circuits. We start by showing how to analyze combinational logic with feedback by drawing a flow table. The flow table shows us which states are stable, which are transient, and which are oscillatory.We then show how to synthesize an asynchronous circuit from a specification by first writing a flow table and then reducing the flow table to logic equations. We see that state assignment is quite critical for asynchronous sequential machines, since it determines when a potential race may occur. We show that some races can be eliminated by introducing transient states.

After the introduction given in this chapter, we continue our discussion of asynchronous circuits in Chapter 27 by looking at latches and flip-flops as examples of asynchronous circuits.

System-level timing is generally driven by the flow of information through the system. Because this information flows through the interfaces between modules, system timing is tightly tied to interface specification. Timing is determined by how modules sequence information over these interfaces. In this chapter we will discuss interface timing and illustrate how the operation of the overall system is sequenced via these interfaces, drawing on the examples introduced in Chapter 21.

How fast will an FSM run? Could making our logic too fast cause our FSM to fail? In this chapter, we will see how to answer these questions by analyzing the timing of our finite-state machines and the flip-flops used to build them.

Finite-state machines are governed by two timing constraints – a maximum delay constraint and a minimum delay constraint. The maximum speed at which we can operate an FSM depends on two flip-flop parameters (the setup time and propagation delay) along with the maximum propagation delay of the next-state logic. On the other hand, the minimum delay constraint depends on the other two flip-flop parameters (hold time and contamination delay) and the minimum contamination delay of the next-state logic. We will see that if the minimum delay constraint is not met, our FSM may fail to operate at any clock speed due to hold-time violations. Clock skew, the delay between the clocks arriving at different flip-flops, affects both maximum and minimum delay constraints.

A pipeline is a sequence of modules, called stages, that each perform part of an overall task. Each stage is like a station along an assembly line – it performs a part of the overall assembly and passes the partial result to the next stage. By passing the incomplete task down the pipeline, each stage is able to start work on a new task before waiting for the overall task to be completed. Thus, a pipeline may be able to perform more tasks per unit time (i.e., it has greater throughput) than a single module that performs the whole task from start to finish.

The throughput, or work done per unit time, of a pipeline is that of the worst stage. Designers must load balance pipelines to avoid idling and wasting resources. Stages that take a variable latency can stall all upstream stages to prevent data propagating down the pipeline. Queues can be used to make a pipeline elastic and tolerate latency variance better than global stall signals.

In this appendix we provide a summary of the VHDL syntax employed in this book. Before using this appendix you should first have read the introductions to VHDL in Section 1.5 and Section 3.6. In addition to this appendix you may find the subject index at the end of this book helpful when looking for information about specific VHDL syntax features. Excellent references documenting the complete VHDL language can be found elsewhere [3, 55]. However, due to the complexity of the VHDL language such references tend to lack detailed discussion of hardware design topics. An abridged summary of the key aspects of VHDL syntax, such as that found in this appendix, can be very helpful when learning hardware design.

Implementing the next-state and output logic of a finite-state machine using a memory array gives a flexible way of realizing an FSM. The function of the FSM can be altered by changing the contents of the memory. We refer to the contents of the memory array as microcode, and a machine realized in this manner is called a microcoded FSM. Each word of the memory array determines the behavior of the machine for a particular state and input combination, and is referred to as a microinstruction.

We can reduce the required size of a microcode memory by augmenting the memory with special logic to compute the next state, and by selectively updating infrequently changing outputs. A single microinstruction can be provided for each state, rather than one for each state × input combination, by adding an instruction sequencer and a branch microinstruction to cause changes in control flow. Bits of the microinstruction can be shared by different functions by defining different microinstruction types for control, output, and other functions.

In this chapter we will see how to build logic circuits (gates) using complementary metal– oxide–semiconductor (CMOS) transistors. We start in Section 4.1 by examining how logic functions can be realized using switches. A series combination of switches performs an AND function while a parallel combination of switches performs an OR function. We can build up more complex switch-logic functions by building more complex series–parallel switch networks.

In Section 4.2 we present a very simple switch-level model of an MOS transistor. CMOS transistors come in two flavors: NMOS and PMOS. For purposes of analyzing the function of logic circuits, we consider an NMOS transistor to be a switch that is closed when its gate is a logic “1” and that passes only a logic “0.” A PMOS transistor is complementary – it is a switch that is closed when its gate is a logic “0” and that passes only a logic “1.” To model the delay and power of logic circuits (which we defer to Chapter 5), we add a resistance and a capacitance to our basic switch. This switch-level model is much simpler than the models used for MOS circuit design, but is perfectly adequate to analyze the functionality and performance of digital logic circuits.

Using our switch-level model, we see how to build gate circuits in Section 4.3 by building a pull-down network of NMOS transistors and a complementary pull-up network of PMOS transistors. A NAND gate, for example, is realized with a series pull-down network of NMOS transistors and a parallel pull-up network of PMOS transistors.

Before we dive into the technical details of digital system design, it is useful to take a high-level look at the way systems are designed in industry today. This will allow us to put the design techniques we learn in subsequent chapters into the proper context. This chapter examines four aspects of contemporary digital system design practice: the design process, implementation technology, computer-aided design tools, and technology scaling.

We start in Section 2.1 by describing the design process – how a design starts with a specification and proceeds through the phases of concept development, feasibility studies, detailed design, and verification. Except for the last few steps, most of the design work is done using English-language documents. A key aspect of any design process is a systematic – and usually quantitative – process of managing technical risk.

Digital designs are implemented on very-large-scale integrated (VLSI) circuits (often called chips) and packaged on printed-circuit boards (PCBs). Section 2.2 discusses the capabilities of contemporary implementation technology.

The design of highly complex VLSI chips and boards is made possible by sophisticated computer-aided design (CAD) tools. These tools, described in Section 2.3, amplify the capability of the designer by performing much of the work associated with capturing a design, synthesizing the logic and physical layout, and verifying that the design is both functionally correct and meets timing.

Approximately every two years, the number of transistors that can be economically fabricated on an integrated-circuit chip doubles. We discuss this growth rate, known as Moore's law, and its implications for digital systems design in Section 2.4.