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The use of thin nitride/oxide (NO) stacked dielectrics is common in DRAM storage node structures today. The cell capacitance can be increased without increasing the cell plate area by decreasing the thickness of the dielectric. Combinations of novel storage node structures, textured electrode surfaces, and very thin NO films (equivalent oxide thickness equal <30 Angstroms) are being characterized for use in 256 Mb and 1 Gb DRAM devices as an alternative to premature use of high k dielectric materials. However, the native oxide formed on the surface of the polysilicon bottom electrode prior to dielectric nitride deposition in a standard LPCVD furnace reactor causes the leakage current and reliability properties of the dielectric to degrade for very thin films. Using a vacuum load-locked RTCVD single-wafer reactor with appropriate in situ ammonia and hydrogen pre-deposition surface conditioning, the native oxide can be eliminated and very thin nitride films of much higher quality can be deposited. A comparison between standard batch LPCVD processing and single-wafer RTCVD for silicon nitride deposition has been done and electrical characteristics (including leakage current and time dependent dielectric breakdown) of the films have been measured. These results indicate that use of NO dielectric films may be extended 1–2 more generations of DRAM devices. This will allow more time for improving the quality of high k dielectric films.
Under a joint development contract with Applied Materials (AMAT) and Texas Instruments (TI), SEMATECH undertook a project (Joint Development Project J100) with a goal of delivering a cost effective, technically advanced Rapid Thermal Processor (RTP). The RTP tool was specified to meet the present and future manufacturing needs of SEMATECH's member companies. The J100 results contained here will focus on the temperature and control performance of the AMAT RTP tool. The J100 results on the temperature measurement and control performance of AMAT's RTP tool using bare backside monitor wafers were presented in part I. In actual manufacturing environments the backside conditions of wafers are not consistent which causes temperature variations during rapid thermal processing. In this experiment, boron monitor wafers with varying backside conditions were used to test the uniformity, repeatability, and stability of the tool. The wafer backside films were fabricated using predictions from emissivity models and were subsequently verified by experimental techniques. In addition, perturbation experiments utilizing boron and arsenic implanted wafers demonstrated a high degree of localized temperature control across the wafers. A 3-sigma temperature variation ranging from 3.0 °C (for wafers with similar backside films) to 6.0 °C (for wafers with varying backside films) was found for all wafers processed during this evaluation. The perturbation experiments, which included a forced temperature offset of two degrees at one of the wafer temperature sensors, resulted in a noticeable change in sheet resistance across the wafer.
Under a joint development contract with Applied Materials (AMAT) and Texas Instruments (TI), SEMATECH undertook a project (Joint Development Project J100) with a goal of delivering a cost effective, technically advanced Rapid Thermal Processor (RTP). The RTP tool was specified to meet the present and future manufacturing needs of SEMATECH's member companies. The J100 results contained here will focus on the temperature and control performance of the AMAT RTP tool. The evaluation methodology included passive data collection (PDC) to check the tool stability, screening experiments to isolate the variable interaction and to define the process window, broad range and narrow range sensitivity studies to determine the sheet resistance dependence on thermal budget for small increments in temperature set point, perturbation experiments to determine localized control, and stability experiments to check for drift and process repeatability. The impact of wafer emissivity on source/drain rapidthermal annealing was evaluated by processing wafers with varying backside films. The PDC experiments demonstrated the tool to be stable. Screening experiments revealed the strong effect of temperature, followed by time, and time-temperature interaction on sheet resistance. Boron implanted (p+/n) wafers were found to be sensitive at a temperature of 1025 °C or less for a 10 second anneal whereas arsenic implanted wafers (n+/p) showed greater sensitivity at temperatures ranging from 1025 °C to 1100 °C for a 10 second anneal.
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