System-on-chip (SoC) technology gives the ability to place multiple functional “systems” on a single silicon chip, cutting the development cycle while increasing product functionality, performance, and quality. In the SoC design methodology, complex tasks or chips are divided into several independent functional blocks and then each block is realized using standard design methodologies with existing CAD tools. The key for a successful SoC endeavor is implementation of the on-chip infrastructure that connects these functional blocks to form a system.

Globally asynchronous, locally synchronous (GALS) SoC design architectures offer a powerful way to solve the interconnect issues with SOC chips that would otherwise arise in a bus-based system such as a globally clocked design with long data transition times, large timing margins, and performance targets that are usually missed.

A GALS-based SoC links islands of locally clocked synchronous logic using an interconnect that has its own local timing, which is decoupled and independent of the surrounding logic blocks. While many methods can be used for asynchronously interconnecting disparate logic blocks, two of the most popular are shared buses with clock domain conversion from each block to the common bus and asynchronous crossbar switches.

The controversial part of GALS, which is based on asynchronous technology, is the great unknown: the asynchronous interconnect. An asynchronous GALS architecture provides the foundation for the massive amount of transistors available in a deep sub-micron (DSM) chip. It is estimated that these devices can support as many as two dozen IP blocks.