Digital system designers usually use hardware description languages (HDLs) to design and model their circuits at several levels of abstraction; Verilog and VHDL have been the most popular. Asynchronous circuit designers, however, often use some form of communicating sequential process (CSP) to model the intended architectural behavior because it has two essential features: channel-based communication and fine-grained concurrency. The former makes data exchange between modules abstract actions. The latter allows one to define nested sequential and concurrent threads in a model. Thus, a practical HDL for high-level asynchronous design should implement the above two constructs. Furthermore, as found in many standard HDLs, the following features are highly desired:

• Support for various levels of abstraction There should be constructs that describe the module at both high and low levels of abstraction (e.g. at module level and at transistor level). This feature enables the modeling of designs at mixed levels of abstraction, which provides incremental verification as units are decomposed into lower levels and also enables arrayed units (e.g. memory banks) to be modeled at high levels of abstraction in order to decrease simulation run-time. Also, this enables the mitered co-simulation of two levels of abstraction, in which the lower-level implementation can be verified against the higher-level, golden, specification with a common input stream.

• Support for synchronous circuits A VLSI chip might consist of both synchronous and asynchronous circuits. The design flow is considerably less complex if a single language can describe both, so that the entire design can be simulated using a single tool. Consequently, the modeling of clocked units should be straightforward.

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