Book contents
- Frontmatter
- Contents
- Acknowledgments
- 1 Introduction
- 2 Channel-based asynchronous design
- 3 Modeling channel-based designs
- 4 Pipeline performance
- 5 Performance analysis and optimization
- 6 Deadlock
- 7 A taxonomy of design styles
- 8 Synthesis-based controller design
- 9 Micropipeline design
- 10 Syntax-directed translation
- 11 Quasi-delay-insensitive pipeline templates
- 12 Timed pipeline templates
- 13 Single-track pipeline templates
- 14 Asynchronous crossbar
- 15 Design example: the Fano algorithm
- Index
- References
7 - A taxonomy of design styles
Published online by Cambridge University Press: 26 February 2010
Book contents
- Frontmatter
- Contents
- Acknowledgments
- 1 Introduction
- 2 Channel-based asynchronous design
- 3 Modeling channel-based designs
- 4 Pipeline performance
- 5 Performance analysis and optimization
- 6 Deadlock
- 7 A taxonomy of design styles
- 8 Synthesis-based controller design
- 9 Micropipeline design
- 10 Syntax-directed translation
- 11 Quasi-delay-insensitive pipeline templates
- 12 Timed pipeline templates
- 13 Single-track pipeline templates
- 14 Asynchronous crossbar
- 15 Design example: the Fano algorithm
- Index
- References
Summary
In addition to the various types of handshaking protocol discussed in Chapter 2, there is a variety of other means to characterize asynchronous design styles, which provide insight into the relative advantages and challenges associated with each design style. In this chapter we discuss several of these forms of taxonomy.
Delay models
The delay model dictates the assumptions made about delays in the gates and wires during the design process. Generally speaking the less restrictive the delay assumptions, the more robust is the design to delay variations caused by a variety of factors such as manufacturing process variations, unpredictable wire lengths, and crosstalk noise. This robustness, however, often comes at a cost such as larger area, lower performance, and/or higher power.
Delay-insensitive design
Delay-insensitive (DI) design is the most robust of all asynchronous circuit delay models. It makes no assumptions on the delay of wires or gates, i.e. they can have zero to infinity delay and can be time varying. Delay-insensitive circuits are thus very robust to all forms of variations.
Although this model is very robust, Martin showed that no practical single-output gate-level delay-insensitive circuits are possible. This result has profound significance. First, to build delay-insensitive circuits the smallest building block must be larger than a single-output gate. As one example, a network of leaf cells that communicate with delay-insensitive channels (e.g. 1-of-N channels) is a delay-insensitive circuit if we consider each leaf cell to be an atomic multi-output gate.
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- A Designer's Guide to Asynchronous VLSI , pp. 116 - 135Publisher: Cambridge University PressPrint publication year: 2010
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